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1. Datasheet 2. Getting Started with the Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts 7. Error Handling 8. IP Core Architecture 9. Transaction Layer Protocol (TLP) Details 10. Throughput Optimization 11. Design Implementation 12. Additional Features 13. Hard IP Reconfiguration 14. Transceiver PHY IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Transaction Layer Packet (TLP) Header Formats B. Lane Initialization and Reversal C. Document Revision History
1.1. Arria V Avalon-ST Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. Debug Features 1.8. IP Core Verification 1.9. Performance and Resource Utilization 1.10. Recommended Speed Grades 1.11. Creating a Design for PCI Express
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Error Signals 4.6. ECRC Forwarding 4.7. Interrupts for Endpoints 4.8. Interrupts for Root Ports 4.9. Completion Side Band Signals 4.10. Transaction Layer Configuration Space Signals 4.11. LMI Signals 4.12. Power Management Signals 4.13. Physical Layer Interface Signals
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. Uncorrectable Internal Error Mask Register 5.8. Uncorrectable Internal Error Status Register 5.9. Correctable Internal Error Mask Register 5.10. Correctable Internal Error Status Register
15.6.1. ebfm_barwr Procedure 15.6.2. ebfm_barwr_imm Procedure 15.6.3. ebfm_barrd_wait Procedure 15.6.4. ebfm_barrd_nowt Procedure 15.6.5. ebfm_cfgwr_imm_wait Procedure 15.6.6. ebfm_cfgwr_imm_nowt Procedure 15.6.7. ebfm_cfgrd_wait Procedure 15.6.8. ebfm_cfgrd_nowt Procedure 15.6.9. BFM Configuration Procedures 15.6.10. BFM Shared Memory Access Procedures 15.6.11. BFM Log and Message Procedures 15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation 15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 15.7.3. Viewing the Important PIPE Interface Signals 15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 15.7.6. Changing between the Hard and Soft Reset Controller
9.2. Transaction Layer Routing Rules
Transactions adhere to the following routing rules:
- In the receive direction (from the PCI Express link), memory and I/O requests that match the defined base address register (BAR) contents and vendor-defined messages with or without data route to the receive interface. The Application Layer logic processes the requests and generates the read completions, if needed.
- In Endpoint mode, received Type 0 Configuration requests from the PCI Express upstream port route to the internal Configuration Space and the Arria V Hard IP for PCI Express generates and transmits the completion.
- The Hard IP handles supported received message transactions (Power Management and Slot Power Limit) internally. The Endpoint also supports the Unlock and Type 1 Messages. The Root Port supports Interrupt, Type 1, and error Messages.
- Vendor‑defined Type 0 and Type 1 Message TLPs are passed to the Application Layer.
- The Transaction Layer treats all other received transactions (including memory or I/O requests that do not match a defined BAR) as Unsupported Requests. The Transaction Layer sets the appropriate error bits and transmits a completion, if needed. These Unsupported Requests are not made visible to the Application Layer; the header and data are dropped.
- For memory read and write request with addresses below 4 GB, requestors must use the 32-bit format. The Transaction Layer interprets requests using the 64‑bit format for addresses below 4 GB as an Unsupported Request and does not send them to the Application Layer. If Error Messaging is enabled, an error Message TLP is sent to the Root Port. Refer to Transaction Layer Errors for a comprehensive list of TLPs the Hard IP does not forward to the Application Layer.
- The Transaction Layer sends all memory and I/O requests, as well as completions generated by the Application Layer and passed to the transmit interface, to the PCI Express link.
- The Hard IP can generate and transmit power management, interrupt, and error signaling messages automatically under the control of dedicated signals. Additionally, it can generate MSI requests under the control of the dedicated signals.
- In Root Port mode, the Application Layer can issue Type 0 or Type 1 Configuration TLPs on the Avalon-ST TX bus.
- The Type 0 Configuration TLPs are only routed to the Configuration Space of the Hard IP and are not sent downstream on the PCI Express link.
- The Type 1 Configuration TLPs are sent downstream on the PCI Express link. If the bus number of the Type 1 Configuration TLP matches the Secondary Bus Number register value in the Root Port Configuration Space, the TLP is converted to a Type 0 TLP.
- For more information about routing rules in Root Port mode, refer to Section 7.3.3 Configuration Request Routing Rules in the PCI Express Base Specification .
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