Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.4.1. Viewing Design Connectivity and Hierarchy

By default, when you open a compiled design, the Design Partition Planner displays the design as a single top-level entity, containing lower-level entities. If the Design Partition Planner has opened the design previously, the design appears in its last state.

Figure 114. Top-Level Entity in the Design Partition Planner

  • To show connectivity between entities, extract entities from the top-level entity by dragging them into the surrounding white space, or by right-clicking an entity and clicking Extract from Parent on the shortcut menu.
    When you extract entities, Design Partition Planner draws the connection bundles between entities, showing the number of connections between pairs of entities.
    Figure 115. Partitioned Design with Connection Bundles

  • To customize the appearance of connection bundles or to set thresholds for connection counts, click View > Bundle Configuration, and set the necessary options in the Bundle Configuration dialog box.
  • To see bundles containing failing paths, open the Timing Analyzer, and then click View > Show Timing Data in the Design Partition Planner. Bundles containing failing paths are displayed in red, as are entities having nodes that reside on failing paths.
  • To see detailed information about the connections in a bundle, right-click the bundle, and then click Bundle Properties to open the Bundle Properties dialog box.
  • To switch between connectivity display mode and hierarchical display mode, click View > Hierarchy Display. Alternatively, click and hold the hierarchy icon in the top-left corner of any entity to switch temporarily to a hierarchy display.