Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023

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Document Table of Contents Spine Clock Limitations

In Intel® Arria® 10 and Intel® Cyclone® 10 GX designs with high clock routing demands, limitations in the Intel® Quartus® Prime software can cause spine clock errors. These limits do not apply to Intel® Stratix® 10 or Intel Agilex® 7 designs.

These errors can occur with designs using multiple memory interfaces and high-speed serial interface (HSSI) channels, especially with PMA Direct mode.

Global clock networks, regional clock networks, and periphery clock networks have an additional level of clock hierarchy known as spine clocks. Spine clocks drive the final row and column clocks to their registers; thus, the clock to every register in the chip is reached through spine clocks. Spine clocks are not directly user controllable.

To reduce these spine clock errors, constrain your design to use your regional clock resources better:

  • If your design does not use Logic Lock regions, or if the Logic Lock regions are not aligned to your clock region boundaries, create additional Logic Lock regions and further constrain your logic.
  • To ensure that the global promotion process uses the correct locations, assign specific pins to the I/Os using these periphery features.
  • By default, some Intel® FPGA IP functions apply a global signal assignment with a value of dual-regional clock. If you constrain your logic to a regional clock region and set the global signal assignment to Regional instead of Dual-Regional, you can reduce clock resource contention.