2.4.1. Design Visualization Tools
The Intel® Quartus® Prime software provides tools that display different graphical representations of your design to help you visualize and optimize placement, connectivity, and routing congestion at various stages of the design cycle.
|Snapshot Viewer||The Compiler can preserve the results of each compilation stage as a snapshot for analysis optimization at each stage. The Snapshot Viewer allows you to easily analyze and optimize compilation results for each snapshot. The Snapshot Viewer provides centralized access to functions and tools that allow you to rapidly analyze clocking, congestion, and correct failing paths and high fan-out nets.|
|RTL Viewer||Provides a schematic representation of the design before synthesis and place-and-route.|
|Technology Map Viewer||Provides a schematic representation of the design implementation in the selected device architecture after synthesis and place-and-route. Optionally, you can include timing information.|
|Chip Planner||Allows you to make floorplan assignments, such as Logic Lock placement constraints, and visualize critical paths and routing congestion. Click the Report Routing Utilization task to display the routing resource congestion.|
|Interface Planner||Simplifies the planning of accurate constraints for physical implementation. Use Interface Planner to prototype interface implementations, plan clocks, and rapidly define a legal device floorplan.|
|Design Partition Planner||Displays design entities, I/O banks, connectivity, design hierarchy, and design partition membership. Design Partition Planner can assist you in visualizing a design's structure for creating effective design partitions.|
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