188.8.131.52. Suspicious Setup
One typical cause is math precision error. For example, 10Mhz/3 = 33.33 ns per period. In three cycles, the time is 99.999 ns vs 100.000 ns. Setting a maximum delay can provide an appropriate setup relationship.
Another cause of failure are paths that must be false by design intent, such as:
- Asynchronous paths handled through FIFOs, or
- Slow asynchronous paths that rely on handshaking for data that remain available for multiple clock cycles.
To prevent the Fitter from having to meet unnecessarily restrictive timing requirements, consider adding false or multicycle path statements.
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