Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023

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Document Table of Contents Improving Register-to-Register Timing

The choice of options and settings to improve the timing margin (slack) or to improve register-to-register timing depends on the failing paths in the design. To achieve the results that best approximate your performance requirements, apply the following techniques and compile the design after each step:
  1. Ensure that your timing assignments are complete and correct. For details, refer to the Initial Compilation: Required Settings section in the Design Optimization Overview chapter.
  2. Review all Design Assistant rule violations and other warning messages from your initial compilation and check for ignored timing assignments. Design Assistant helps to identify and correct any invalid timing constraints.
  3. Apply netlist synthesis optimization options.
  4. To optimize for speed, apply the following synthesis options:
    • Optimize Synthesis for Speed, Not Area
    • Flatten the Hierarchy During Synthesis
    • Set the Synthesis Effort to High
    • Prevent Shift Register Inference
    • Use Other Synthesis Options Available in Your Synthesis Tool
  5. To optimize for performance, turn on Advanced Physical Optimization
  6. Try different Fitter seeds. If only a small number of paths are failing by small negative slack, then you can try with a different seed to find a fit that meets constraints in the Fitter seed noise.
    Note: Omit this step if a large number of critical paths are failing, or if the paths are failing by a long margin.
  7. To control placement, make Logic Lock assignments.
  8. Modify your design source code to fix areas of the design that are still failing timing requirements by significant amounts.
  9. Make location assignments, or as a last resort, perform manual placement by back-annotating the design.
    You can use Design Space Explorer II (DSE) to automate the process of running different compilations with different settings.
    If these techniques do not achieve performance requirements, additional design source code modifications might be required.