Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023

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Document Table of Contents Use PLLs to Shift Clock Edges

Using a PLL typically improves I/O timing automatically. If the timing requirements are still not met, most devices allow the PLL output to be phase shifted to change the I/O timing. Shifting the clock backwards gives a better tH at the expense of tSU, while shifting it forward gives a better tSU at the expense of tH. You can use this technique only in devices that offer PLLs with the phase shift option.
Figure 57. Shift Clock Edges Forward to Improve tSU at the Expense of tH

You can achieve the same type of effect in certain devices by using the programmable delay called Input Delay from Dual Purpose Clock Pin to Fan-Out Destinations.