Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023

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2.2.2. Initial Timing Constraint Guidelines

Before running initial compilation or timing analysis, specify realistic timing requirements. Specifying more stringent timing requirements than the design requires causes the Compiler to expend effort to increase performance at the expense of resource usage, power utilization, or compilation time.

Click Tools > Timing Analyzer then click the Constraints menu to enter constraints in the GUI, such as defining the clock signals. Alternatively, you can specify timing constraints directly in an .sdc file.

Figure 3. Create Clock Dialog Defines Clock Constraints

Specifying realistic and comprehensive timing requirements up front helps the Compiler to achieve the best results for the following reasons:

  • Comprehensive timing assignments enable the Compiler to work hardest to optimize the performance of the timing-critical parts of the design. This optimization can also save area or power utilization in non-critical parts of the design.
  • Enables physical synthesis optimizations based on the comprehensive timing requirements.
Figure 4. Timing Analyzer Shows Failing Paths in Red

Following compilation and timing analysis, the Compilation Report reports whether the design meets the timing requirements. You can then use the Intel® Quartus® Prime Timing Analyzer to fine tune constraints and report detailed information about all timing paths.