Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023

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2.3.2. Critical Path Delay Reduction Trade-Offs

To meet complex timing requirements involving multiple clocks, routing resources, and area constraints, the Intel® Quartus® Prime software offers a close interaction between synthesis, floorplan editing, place-and-route, and timing analysis processes.

By default, the Intel® Quartus® Prime Fitter works to meet the timing requirements, and reduces fitting effort once the requirements are met. Therefore, specifying realistic constraints is crucial for achieving timing closure.

Under-constraining your design can lead to sub-optimal results. Over-constraining your design might cause the Fitter to over-optimize non-critical paths at the expense of true critical paths. Over-constraining the design may also increase area and compilation time.

When designs have very high resource usage, the Fitter may struggle to find a legal placement. In such circumstances, the Fitter automatically modifies settings to try to trade off performance for area.

In high-density FPGAs, routing accounts for a major part of critical path timing. Because of this, duplicating or retiming logic can allow the Fitter to reduce delay on critical paths. The Intel® Quartus® Prime software offers push-button netlist optimizations and physical synthesis options that can improve design performance at the expense of considerable increases of compilation time and area.

Figure 6. Register Optimization

Turn on only those options that help you keep reasonable compilation times and resource usage. Alternately, you can modify the HDL to manually duplicate or adjust the timing logic.