Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023
Document Table of Contents Viewing Available Clock Networks in Chip Planner

When you enable a clock region layer in the Layers Settings pane, you display the areas of the chip that are driven by global and regional clock networks.
When the selected device does not contain a given clock region, the option for that category is unavailable in the dialog box.

Depending on the clock layers that you activate in the Layers Settings pane, the Chip Planner displays regional and global clock regions in the device, and the connectivity between clock regions, pins, and PLLs.

Note: The Intel® Stratix® 10 and Intel Agilex® 7 device clocking architecture does not include regional clocks nor spine clocks.

Clock regions appear as rectangular overlay boxes with labels indicating the clock type and index. Select a clock network region by clicking the clock region. The clock-shaped icon at the top-left corner indicates that the region represents a clock network region.

Figure 74. Clock Regions

Spine/sector clock regions have a dotted vertical line in the middle. This dotted line indicates where two columns of row clocks meet in a sector clock.

To change the color in which the Chip Planner displays clock regions, select Tools > Options > Colors > Clock Regions.

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