Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 4/03/2023
Public
Document Table of Contents

5.2.3.5. Guideline: Use Register Packing

The Auto Packed Registers option implements the functions of two elements into one logic element by combining the register of one element, in which only the register is used with the LUT of another element, in which only the LUT is used.

DSP Register Packing Entity Assignment

In addition, you can control DSP register packing at the entity level by specifying the DSP Register Packing entity assignment in the Assignment Editor, or with the corresponding DSP_REGISTER_PACKING assignment in the project .qsf. DSP Register Packing specifies how aggressively the Fitter optimizes DSP performance by automatically packing registers into the internal registers of the specified DSP blocks. With the default Balanced setting, the Fitter packs registers into the specified DSP blocks that improve timing. With Always enabled, the Fitter aggressively pack registers into the specified DSP blocks, unless your constraints or other legality restrictions prevent packing. With Disable enabled, registers do not pack into the specified DSP blocks. The following is the equivalent .qsf assignment:

set_instance_assignment -name DSP_REGISTER_PACKING -to \
<to> -entity <name> <value>

DSP_REGISTER_PACKING_LEVEL Entity Assignment

In addition, you can enter the DSP_REGISTER_PACKING_LEVEL entity assignment directly in the project .qsf to specify the maximum number of register stages desired for a specific DSP. DSP_REGISTER_PACKING_LEVEL specifies the maximum number of registers that you want to pack in the specified DSP instance. The following are DSP_REGISTER_PACKING_LEVEL setting values:

  • 0—equivalent to disabling DSP register packing operation of the DSP.
  • 1—the Fitter tries to pack one layer of registers from the DSP's input side.
  • 2—the Fitter tries to add an additional layer of registers from the DSP's output side.
  • 3 or 4—the Fitter tries to add one or two layers of the pipeline registers from the input side.

If the Compiler cannot implement the packing level you specify, the Compiler issues a warning message indicating that the assignment is not respected. the Fixed Point DSP Register Packing Details report also describes the reasons the packing level cannot be met. The following is the equivalent .qsf assignment:

set_instance_assignment -name DSP_REGISTER_PACKING_LEVEL -to \
<to> -entity <entity name> <value>

Fixed Point DSP Register Packing Summary Report and Fixed Point DSP Register Packing Details Report

After running the Compiler's Plan stage, the Compilation Report includes the Fixed Point DSP Register Packing Summary report, and the Fixed Point DSP Register Packing Details report. These reports provide information about the use of DSP blocks in your design, including DSP register packing data. The summary report lists how many DSP blocks are fully registered, partially registered, or unregistered.

The Fixed Point DSP Register Packing Details report also indicates the names of the registers packed into register banks, the register usage (fully registered, partially registered, or unregistered), and the reasons preventing any register packing. Viewing these register name details in the report allows you to readily identify registers for packing assignments.

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