Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.6.2. Reset Controller

Platform Designer automatically inserts a reset controller block if the input reset source does not have a reset request, but the connected reset sink requires a reset request.

The Reset Controller has the following parameters that you can specify to customize its behavior:

  • Number of inputs— Indicates the number of individual reset interfaces the controller ORs to create a signal reset output.
  • Output reset synchronous edges—Specifies the level of synchronization. You can select one the following options:
    • None—The reset is asserted and deasserted asynchronously. You can use this setting if you have designed internal synchronization circuitry that matches the reset style required for the IP in the system.
    • Both—The reset is asserted and deasserted synchronously.
    • Deassert—The reset is deasserted synchronously and asserted asynchronously.
  • Synchronization depth—Specifies the number of register stages the synchronizer uses to eliminate the propagation of metastable events.
  • Reset request—Enables reset request generation, which is an early signal that is asserted before reset assertion. The reset request is used by blocks that require protection from asynchronous inputs, for example, M20K blocks.

Platform Designer automatically inserts reset synchronizers under the following conditions:

  • More than one reset source is connected to a reset sink
  • There is a mismatch between the reset source’s synchronous edges and the reset sinks’ synchronous edges