Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

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7.1.4. Avalon® Memory Mapped Unaligned Burst Expansion Bridge Intel® FPGA IP

The Avalon® Memory Mapped Unaligned Burst Expansion Bridge Intel® FPGA IP aligns read burst transactions from hosts connected to its agent interface, to the address space of agents connected to its host interface. This alignment ensures that all read burst transactions are delivered to the agent as a single transaction.
Figure 207.  Avalon® Memory Mapped Unaligned Burst Expansion Bridge Intel® FPGA IP


You can use the Avalon® Unaligned Burst Expansion Bridge to align read burst transactions from hosts that have narrower data widths than the target agents. Using the bridge for this purpose improves bandwidth utilization for the host-agent pair, and ensures that unaligned bursts are processed as single transactions rather than multiple transactions.

Note: Do not use the Avalon® Memory Mapped Unaligned Burst Expansion Bridge if any connected agent has read side effects from reading addresses that are exposed to any connected host's address map. This bridge can cause read side effects due to alignment modification to read burst transaction addresses.
Note: The Avalon® Memory Mapped Unaligned Burst Expansion Bridge does not support VHDL simulation.