Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

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5.7.1.2. Removing Unnecessary Connections to Minimize Interconnect Logic

The number of connections between host and agent interfaces affects the fMAX of your system. Every host interface that you connect to an agent interface increases the width of the multiplexer width. As a multiplexer width increases, so does the logic depth and width that implements the multiplexer in the FPGA. To improve system performance, connect hosts and agents only when necessary.

When you connect a host interface to many agent interfaces, the multiplexer for the read data signal grows. Avalon typically uses a readdata signal. AXI read data signals add a response status and last indicator to the read response channel using rdata, rresp, and rlast. Additionally, bridges help control the depth of multiplexers.