Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

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6.15.10.1. Synchronous Interface

All transfers of an Avalon® Streaming connection occur synchronous to the rising edge of the associated clock signal. All outputs from a source interface to a sink interface, including the data, channel, and error signals, must be registered on the rising edge of clock. Inputs to a sink interface do not have to be registered. Registering signals at the source facilitates high-frequency operation.

Table 110.   Avalon® Streaming Credit Interface Properties

Property Name

Default Value

Legal Value

Description

associatedClock

1

Clock interface

The name of the Avalon® Clock interface to which this Avalon® Streaming interface is synchronous.

associatedReset

1

Reset interface

The name of the Avalon® Reset interface to which this Avalon® Streaming interface is synchronous.

dataBitsPerSymbol

8

1 – 8192

Defines the number of bits per symbol. For example, byte-oriented interfaces have 8-bit symbols. This value is not restricted to be a power of 2.

symbolsPerBeat

1

1 – 8192

The number of symbols that are transferred on every valid cycle.

maxCredit

256

1-256

The maximum number of credits that a data interface can support.

errorDescriptor

0

List of strings

A list of words that describe the error associated with each bit of the error signal. The length of the list must be the same as the number of bits in the error signal. The first word in the list applies to the highest order bit. For example, “crc, overflow" means that bit[1] of error indicates a CRC error. Bit[0] indicates an overflow error.

firstSymbolInHighOrderBits

true

true, false

When true, the first-order symbol is driven to the most significant bits of the data interface. The highest-order symbol is labeled D0 in this specification. When this property is set to false, the first symbol appears on the low bits. D0 appears at data[7:0]. For a 32-bit bus, if true, D0 appears on bits[31:24].

maxChannel

0

0

The maximum number of channels that a data interface can support.