Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.5.3. Avalon® Streaming Splitter Intel® FPGA IP Parameters

Table 180.   Avalon® Streaming Splitter Intel® FPGA IP Parameters

Parameter

Legal Values

Default Value

Description

Number Of Outputs

1 to 16

2

The number of output interfaces. Platform Designer supports 1 for some systems where no duplicated output is required.

Qualify Valid Out

Enabled, Disabled

Enabled

If enabled, the out_valid signal of all output interfaces is gated when back pressure is applied.

Data Width

1–512

8

The width of the data on the Avalon® streaming data interfaces.

Bits Per Symbol

1–512

8

The number of bits per symbol for the input and output interfaces. For example, byte-oriented interfaces have 8-bit symbols.

Use Packets

Enabled, Disabled

Disabled

Enable support of data packet transfers. Packet support includes the startofpacket, endofpacket, and empty signals.

Use Channel

Enabled, Disabled

Disabled

Enable the channel signal.

Channel Width

0-8

1

The width of the channel signal on the data interfaces. This parameter is disabled when Use Channel is set to 0.

Max Channels

0-255

1

The maximum number of channels that a data interface can support. This parameter is disabled when Use Channel is set to 0.

Use Error

Enabled, Disabled

Disabled

Enable the error signal.

Error Width

0–31

1

The width of the error signal on the output interfaces. A value of 0 indicates that the IP is not using the error signal. This parameter is disabled when Use Error is set to 0.