Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.4.2.2. IRQ Mapper

Platform Designer inserts the IRQ Mapper Intel® FPGA IP automatically during generation. The IRQ Mapper converts individual interrupt wires to a bus, and then maps the appropriate IRQ priority number onto the bus.

You can specify the following parameter values:

Table 76.  IRQ Mapper Parameters
Parameter Values Description

Number of receivers

1-2048 Specifies the number of Avalon receiver signals on the bus.
Sender interrupt width 1-2048 Specifies the width of the Avalon sender signal bus.
Use synchronous resets On|Off Resets signal synchronously. This option is Off by default.
Remove Clock and Reset Ports On|Off Removes the clock and reset ports from the component. If both Use synchronous resets and Remove Clock and Reset Ports are on, Platform Designer displays an error.

By default, the interrupt sender connected to the receiver0 interface of the IRQ mapper is the highest priority, and sequential receivers are successively lower priority. You can modify the interrupt priority of each IRQ wire by modifying the IRQ priority number in Platform Designer under the IRQ column. The modified priority is reflected in the IRQ_MAP parameter for the auto-inserted IRQ Mapper.

Figure 190. IRQ Column in Platform Designer Circled in the IRQ column are the default interrupt priorities allocated for the CPU subsystem.