Agilex™ 7 Hard Processor System Component Reference Manual
                    
                        ID
                        683581
                    
                
                
                    Date
                    10/08/2025
                
                
                    Public
                
            
                        
                        
                            
                                3.1. Simulation Flows
                            
                            
                        
                            
                                3.2. Clock and Reset Interfaces
                            
                            
                        
                            
                            
                                3.3. FPGA-to-HPS AXI* Slave Interface
                            
                        
                            
                            
                                3.4. HPS-to-FPGA AXI* Master Interface
                            
                        
                            
                            
                                3.5. Lightweight HPS-to-FPGA AXI* Master Interface
                            
                        
                            
                            
                                3.6. HPS-to-FPGA MPU Event Interface
                            
                        
                            
                            
                                3.7. Interrupts Interface
                            
                        
                            
                            
                                3.8. HPS-to-FPGA Debug APB Interface
                            
                        
                            
                            
                                3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
                            
                        
                            
                            
                                3.10. HPS-to-FPGA Cross-Trigger Interface
                            
                        
                            
                            
                                3.11. HPS-to-FPGA Trace Port Interface
                            
                        
                            
                            
                                3.12. FPGA-to-HPS DMA Handshake Interface
                            
                        
                            
                            
                                3.13. General Purpose Input Interface
                            
                        
                            
                            
                                3.14. EMIF Conduit
                            
                        
                            
                            
                                3.15. Simulating the Agilex™ 7 HPS Component Revision History
                            
                        
                    
                4.4.1. Questa*-Altera® FPGA Edition Simulation Steps
- Use the following command to change directory to the Mentor Graphics* testbench simulation directory: cd <project directory>/simple_tb/simple_tb/sim/mentor/.
- Create a new file and name it my_msim_setup.do. Edit the file with the following content:
    set TOP_LEVEL_NAME simple_tb ### set QSYS_SIMDIR <script generation output directory> set QSYS_SIMDIR ./.. ### source msim_setup.tcl source $QSYS_SIMDIR/mentor/msim_setup.tcl ensure_lib libraries ensure_lib libraries/work vmap work libraries/work ### Compile dev_com com vlib work vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../my_simple_tb.sv vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_lwh2f.sv vlog -sv -timescale 1ns/1ns -L altera_lnsim_ver ../test_h2f.sv ### Simulate elab_debug add wave -group LWH2F /simple_tb/simple_inst/intel_agilex_hps_0/intel_agilex_hps_0/fpga_interfaces/hps_inst/s2f_module/lwh2f_bfm_gen/lwh2f_axi4_manager_inst/* add wave -group H2F /simple_tb/simple_inst/intel_agilex_hps_0/intel_agilex_hps_0/fpga_interfaces/hps_inst/s2f_module/h2f_bfm_gen/h2f_axi4_manager_inst/* ### Run the simulation. run -all
- Set up your developer environment with the proper resources. The Questa*-Altera® FPGA Starter Edition is free, however it requires a zero-cost license. For comprehensive information for downloading, installing, and licensing Altera FPGA software, refer to the Altera® FPGA Software Installation and Licensing
- Run the simulation script by being in the  Mentor Graphics*  testbench simulation directory and executing the simulation command:
    - cd <project directory>/simple_tb/simple_tb/sim/mentor/
- vsim -do my_msim_setup.do
 The following figure shows the simulation output from this example.Figure 43. Example of Simulation Output