Intel® Arria® 10 SoC UEFI Boot Loader User Guide

ID 683536
Date 12/15/2017
Document Table of Contents

1.5.1. Compiling the Hardware Design

Task Time: 30 Minutes

If you make any changes, you must re-compile the design that is packaged in the SoC FPGA EDS. Otherwise, you can directly work with the pre-compiled design. As an example, the following sections describe how to compile the hardware design packaged in the SoC FPGA EDS.