Intel® Arria® 10 SoC UEFI Boot Loader User Guide

ID 683536
Date 12/15/2017
Document Table of Contents

1.4. Boot Flow Overview

A typical UEFI boot flow runs entirely on the on-chip memory of the HPS and is a default selection for booting a bare-metal application and RTOS. UEFI replaces the MPL boot loader on Cyclone® V and Arria® V devices.

UEFI boot loader tasks include:

  • Initializing DDR SDRAM memory
  • Configuring low level hardware such as PLL, IOs, and pin-muxing
  • Supporting basic hardware diagnostic features
  • Fetching subsequent boot software such as the operating system package or kernel image.
Figure 1. Typical UEFI Boot Flow

Pre-DDR diagnostic boot flow boots into a diagnostic utility called Pit Stop. This utility executes from the on-chip memory of the HPS and debugs and performs diagnosis prior to booting the next stage. The PcdEnablePitStopUtility token in the Arria10SoCPkg.dsc file enables the Pit Stop utility.

Figure 2. Pre-DDR Diagnostic Boot Flow

Post-DDR boot stage, also known as UEFI DXE phase, supports extended UEFI functionality. This boot flow allows you to access a broad range of pre-existing UEFI utilities already developed by the open source community.

Booting the DXE phase requires DDR SDRAM to be ready. In the post-DDR extended boot flow, you can boot into the UEFI shell to access features such as TFTP file transfer, scripting and running your UEFI applications. You can continue to boot after the UEFI shell by using commands such as:
  • runaxf to boot to an ELF binary
  • Linux Loader to continue booting in Linux
Note: SoC FPGA EDS 16.0 and above supports booting Linux.
Figure 3. Post-DDR Extended Boot Flow