1.1. Acronyms and Definitions
1.2. Recommended System Requirements
1.3. Installation Folders
1.4. Boot Flow Overview
1.5. Getting Started
1.6. Enabling the UEFI DXE Phase and the UEFI Shell
1.7. Using the Network Feature Under the UEFI Shell
1.8. Creating your First UEFI Application
1.9. Using Arm* DS-5* Intel® SoC FPGA Edition (For Windows* Only)
1.10. Pit Stop Utility Guide
1.11. Porting HWLIBs to UEFI Guidelines
1.12. Tera Term Installation
1.13. Minicom Installation
1.14. Win32DiskImager Tool Installation
1.15. TFTPd64 By Ph.Jounin Installation
1.16. Revision History of Intel® Arria® 10 SoC UEFI Boot Loader User Guide
1.5.1. Compiling the Hardware Design
1.5.2. Generating the Boot Loader and Device Tree for UEFI Boot Loader
1.5.3. Building the UEFI Boot Loader
1.5.4. Creating an SD Card Image
1.5.5. Creating a QSPI Image
1.5.6. Booting the Board with SD/MMC
1.5.7. Booting the Board with QSPI
1.5.8. Early I/O Release
1.5.9. Booting Linux* Using the UEFI Boot Loader
1.5.10. Debugging an Example Project
1.5.11. UEFI Boot Loader Customization
1.5.12. Enabling Checksum for the FPGA Image
1.5.13. NAND Bad Block Management
1.5.8. Early I/O Release
Task time: 30 minutes
Early I/O release enables DDR functioning prior to programming the core raw binary file (RBF). This feature provides a faster boot time because the shared I/O and hard memory controller I/O are configured and released for immediate access by the HPS. Early I/O release also enables availability of the shared I/O so that device can obtain the core RBF from the TFTP server instead of flash. The CSS then configures and releases the FPGA fabric allowing the HPS to have access. Early I/O release also provides early response in time critical systems.
The peripheral RBF configures shared I/O, hard memory controller I/O, and hard memory controller settings such as memory type, frequency and timings. The core RBF configures the FPGA fabric, FPGA I/O and FPGA PLL settings. You can choose to combine the peripheral and core RBF into one RBF that configures both the FPGA fabric and the I/O Control Shift registers (IOCSRs). Using a combined RBF creates a performance penalty that is much slower than splitting the RBFs. When you split the RBFs, the core RBF loads into SDRAM instead of on-chip RAM from flash providing a larger data transfer block and boosting performance.