Intel® Stratix® 10 Hard Processor System Component Reference Manual
ID
683516
Date
2/10/2023
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the HPS Component Revision History
2.2. FPGA Interfaces
The FPGA Interfaces tab allows you to specify options for the primary interfaces between the FPGA and the HPS. The following groups in this tab are:
- General
- HPS FPGA AXI Bridges
- HPS Boot Source
- DMA Peripheral Request
- Interrupts
Figure 2. HPS Component Parameter Editor FPGA Interfaces Tab