Intel® Stratix® 10 Hard Processor System Component Reference Manual
ID
683516
Date
2/10/2023
Public
3.1. Simulation Flows
3.2. Clock and Reset Interfaces
3.3. FPGA-to-HPS AXI* Slave Interface
3.4. HPS-to-FPGA AXI* Master Interface
3.5. Lightweight HPS-to-FPGA AXI* Master Interface
3.6. HPS-to-FPGA MPU Event Interface
3.7. Interrupts Interface
3.8. HPS-to-FPGA Debug APB Interface
3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface
3.10. HPS-to-FPGA Cross-Trigger Interface
3.11. HPS-to-FPGA Trace Port Interface
3.12. FPGA-to-HPS DMA Handshake Interface
3.13. General Purpose Input Interface
3.14. EMIF Conduit
3.15. Simulating the HPS Component Revision History
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
The system trace microcell hardware events interface allows logic in the FPGA to insert messages into the trace stream.
For more information about the System Trace Macrocell Hardware Events interface, refer to the “CoreSight Debug and Trace” chapter in the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.
Turning on the Enable System Trace Macrocell Hardware Events option enables the f2h_stm_hw_events conduit, which is comprised of the single bus f2h_stm_hwevents[42…0].
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