Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

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ID 683358
Date 1/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Cyclone® 10 GX 2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX 3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX 4. CvP Driver and Registers A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide
1. CvP Initialization in Intel® Cyclone® 10 GX x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Cyclone® 10 GX Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX x
3.1. Generating the Synthesis HDL Files for Intel® Cyclone® 10 GX PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Modifying MSEL/DIP switch on Intel® Cyclone® 10 GX Dev-Kit 3.5.4. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Intel® -defined Vendor Specific Capability Header Register 4.3.2. Intel® -defined Vendor Specific Header Register 4.3.3. Intel® Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
1. CvP Initialization in Intel® Cyclone® 10 GX
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX
4. CvP Driver and Registers
A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

3.4. Splitting the SOF File

Follow these steps to split your .sof file into separate images for the periphery and core logic.

  1. After the .sof file is generated, under File menu, select Convert Programming Files.
  2. Under Output programming file section, specify the following parameters:
    Table 5.  Parameters: Output Programming File Tab
    Parameter Value
    Programming file type JTAG Indirect Configuration File (*.jic)
    Configuration device EPCQL1024
    Mode Active Serial
    File name *.periph.jic
    Create Memory Map File Turn this option on.
    Create CvP files Turn this option on. This box is greyed out until you specify the SOF Data file under Input files to convert.

  3. Under Input files to convert, specify the following parameters:
    Table 6.  Parameters: Input Files to Convert Tab
    Parameter Value
    Flash Loader 10CX220YF780E5G
    SOF Data *.sof
  4. Make sure to turn on the Create CvP files.
    Note: If you do not check this box, the Intel® Quartus® Prime software does not create separate files for the periphery and core images.
    Figure 9. Illustrating the above specified options in the Covert Programming File GUI
  5. Click Generate to create *.periph.jic and *.core.rbf files.
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