Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

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ID 683358
Date 1/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Cyclone® 10 GX 2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX 3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX 4. CvP Driver and Registers A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide
1. CvP Initialization in Intel® Cyclone® 10 GX x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Cyclone® 10 GX Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX x
3.1. Generating the Synthesis HDL Files for Intel® Cyclone® 10 GX PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Modifying MSEL/DIP switch on Intel® Cyclone® 10 GX Dev-Kit 3.5.4. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Intel® -defined Vendor Specific Capability Header Register 4.3.2. Intel® -defined Vendor Specific Header Register 4.3.3. Intel® Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
1. CvP Initialization in Intel® Cyclone® 10 GX
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX
4. CvP Driver and Registers
A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

1.2. CvP System

The following figure shows the required components for a CvP system.

Figure 1. CvP Block Diagram

A CvP system typically consists of an FPGA, a PCIe host, and a configuration device.

  1. The configuration device is connected to the FPGA using the conventional configuration interface. The configuration interface can be any of the supported schemes, such as active serial (AS), passive serial (PS), or fast passive parallel (FPP). The choice of the configuration device depends on your chosen configuration scheme.
  2. PCIe Hard IP block for CvP and other PCIe applications.

It must be configured as an Endpoint.

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