Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

Download PDF
ID 683358
Date 1/02/2018
Public
Document Table of Contents
Document Table of Contents x
1. CvP Initialization in Intel® Cyclone® 10 GX 2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX 3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX 4. CvP Driver and Registers A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide
1. CvP Initialization in Intel® Cyclone® 10 GX x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Support for Intel® Cyclone® 10 GX Devices 1.4. CvP Initialization 1.5. CvP Compression and Encryption Features 1.6. CvP Pins
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX x
2.1. Designing CvP for an Open System 2.2. Designing CvP for a Closed System
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX x
3.1. Generating the Synthesis HDL Files for Intel® Cyclone® 10 GX PCI Express IP Core 3.2. Setting up the CvP Parameters in Device and Pin Options 3.3. Compiling the Design 3.4. Splitting the SOF File 3.5. Bringing up the Hardware
3.5. Bringing up the Hardware x
3.5.1. Installing Jungo WinDriver in Windows Systems 3.5.2. Installing Jungo WinDriver in Linux Systems 3.5.3. Modifying MSEL/DIP switch on Intel® Cyclone® 10 GX Dev-Kit 3.5.4. Programming CvP Images
4. CvP Driver and Registers x
4.1. CvP Driver Support 4.2. CvP Driver Flow 4.3. VSEC Registers for CvP
4.3. VSEC Registers for CvP x
4.3.1. Intel® -defined Vendor Specific Capability Header Register 4.3.2. Intel® -defined Vendor Specific Header Register 4.3.3. Intel® Marker Register 4.3.4. CvP Status Register 4.3.5. CvP Mode Control Register 4.3.6. CvP Data Registers 4.3.7. CvP Programming Control Register 4.3.8. Uncorrectable Internal Error Status Register 4.3.9. Uncorrectable Internal Error Mask Register 4.3.10. Correctable Internal Error Status Register 4.3.11. Correctable Internal Error Mask Register
1. CvP Initialization in Intel® Cyclone® 10 GX
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX
4. CvP Driver and Registers
A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

4.3.5. CvP Mode Control Register

Table 13.  CvP Mode Control Register (Byte Offset: 0x220)
Bits Name Reset Value Access Description
[31:16] — 0x0000 RO Reserved.
[15:8] CVP_NUMCLKS 0x00 RW

This is the number of clocks to send for every CvP data write. This is also known as CDRATIO (clock to data ratio).

Set this field to one of the values below depending on your configuration image:

  • 0x01 for uncompressed and unencrypted images
  • 0x04 for uncompressed and encrypted images
  • 0x08 for all compressed images
[7:3] — 0x0 RO Reserved.
[2] CVP_FULLCONFIG 1'b0 RW A value of 1 indicates a request to the control block to reconfigure the entire FPGA including the Hard IP for PCI Express and bring the PCIe link down.
[1] HIP_CLK_SEL 1'b0 RW Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The following encodings are defined:
  • 1: Selects internal clock from PMA which is required for CVP_MODE.
  • 0: Selects the clock from soft logic fabric. This setting should only be used when the fabric is configured in USER_MODE with a configuration file that connects the correct clock.
To ensure that there is no clock switching during CvP, you should only change this value when the Hard IP for PCI Express has been idle for 10 µs and wait 10 µs after changing this value before resuming activity.
[0] CVP_MODE 1'b0 RW Controls whether the Hard IP for PCI Express is in CVP_MODE or normal mode. The following encodings are defined:
  • 1: CVP_MODE is active. Signals to the FPGA control block active and all TLPs are routed to the Configuration Space. This CVP_MODE cannot be enabled if CVP_EN = 0.
  • 0: The IP core is in normal mode and TLPs are route to the FPGA fabric.
Level Two Title