Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

ID 683358
Date 1/02/2018
Document Table of Contents

4.3.5. CvP Mode Control Register

Table 13.  CvP Mode Control Register (Byte Offset: 0x220)
Bits Name Reset Value Access Description
[31:16] 0x0000 RO Reserved.
[15:8] CVP_NUMCLKS 0x00 RW

This is the number of clocks to send for every CvP data write. This is also known as CDRATIO (clock to data ratio).

Set this field to one of the values below depending on your configuration image:

  • 0x01 for uncompressed and unencrypted images
  • 0x04 for uncompressed and encrypted images
  • 0x08 for all compressed images
[7:3] 0x0 RO Reserved.
[2] CVP_FULLCONFIG 1'b0 RW A value of 1 indicates a request to the control block to reconfigure the entire FPGA including the Hard IP for PCI Express and bring the PCIe link down.
[1] HIP_CLK_SEL 1'b0 RW Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The following encodings are defined:
  • 1: Selects internal clock from PMA which is required for CVP_MODE.
  • 0: Selects the clock from soft logic fabric. This setting should only be used when the fabric is configured in USER_MODE with a configuration file that connects the correct clock.
To ensure that there is no clock switching during CvP, you should only change this value when the Hard IP for PCI Express has been idle for 10 µs and wait 10 µs after changing this value before resuming activity.
[0] CVP_MODE 1'b0 RW Controls whether the Hard IP for PCI Express is in CVP_MODE or normal mode. The following encodings are defined:
  • 1: CVP_MODE is active. Signals to the FPGA control block active and all TLPs are routed to the Configuration Space. This CVP_MODE cannot be enabled if CVP_EN = 0.
  • 0: The IP core is in normal mode and TLPs are route to the FPGA fabric.