Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

ID 683358
Date 1/02/2018
Document Table of Contents

4.2. CvP Driver Flow

The following figure shows the flow of the provided CvP driver. The flow assumes that the FPGA is powered up and the control block has already configured the FPGA with the periphery image, which is indicated by the CVP_EN bit in the CvP status register.

As this figure indicates, the third step of the Start Teardown Flow requires 244 dummy configuration writes to the CVP DATA register or 244 memory writes to an address defined by a memory space BAR for this device. Memory writes are preferred because they are higher throughput than configuration writes. The dummy 244 memory writes cause a 2 ms delay, allowing the control block to complete required operations.

Figure 12. CvP Driver Flow

For high density devices such as Intel® Cyclone® 10 GX, it may be necessary to wait up to 500 ms for the CvP status register bit assertion.