2.1. Designing CvP for an Open System
FPGA Power Supplies Ramp Time Requirement
For an open system, you must ensure that your design adheres to the FPGA power supplies ramp-up time requirement.
The power-on reset (POR) circuitry keeps the FPGA in the reset state until the power supply outputs are in the recommended operating range. A POR event occurs from when you power up the FPGA until the power supplies reach the recommended operating range within the maximum power supply ramp time, tRAMP . If tRAMP is not met, the device I/O pins and programming registers remain tri-stated, during which device configuration could fail.
For CvP, the total tRAMP must be less than 10 ms, from the first power supply ramp-up to the last power supply ramp-up. You must select fast POR by setting the PORSEL pin to high. The fast POR delay time is in the range of 4–12 ms, allowing sufficient time after POR for the PCIe link to start initialization and configuration.
PCIe Wake-Up Time Requirement
For an open system, you must ensure that the PCIe link meets the PCIe wake-up time requirement as defined in the PCI Express CARD Electromechanical Specification. The transition from power-on to the link active (L0) state for the PCIe wake-up timing specification must be within 200 ms. The timing from FPGA power-up until the Hard IP for PCI Express IP Core in the FPGA is ready for link training must be within 120 ms.
PCIe Wake-Up Time Requirement for CvP Initialization
For CvP initialization mode, the Hard IP for PCI Express IP core is guaranteed to meet the 120 ms requirement because the periphery image configuration time is significantly less than the full FPGA configuration time. Therefore, you can choose any of the conventional configuration schemes for the periphery image configuration.
To ensure successful configuration, all POR-monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp-up time. The PERST# signal indicates when the FPGA power supplies are within their specified voltage tolerances and the REFCLK is stable. The embedded hard reset controller triggers after the internal status signal indicates that the periphery image has been loaded. This reset does not trigger off of PERST#. For CvP initialization mode, the PCIe link supports the FPGA core image configuration and PCIe applications in user mode.
|Timing Sequence||Timing Range (ms)||Description|
|a||10||Maximum ramp-up time requirement for all POR-monitored power supplies in the FPGA to reach their respective operating range.|
|b||4–12||FPGA POR delay time.|
|c||100||Minimum PERST# signal active time from the host.|
|d||20||Minimum PERST# signal inactive time from the host before the PCIe link enters training state.|
|e||120||Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode.|
|f||100||Maximum time PCIe device must enter L0 after PERST# is deasserted.|
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