Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

ID 683358
Date 1/02/2018
Document Table of Contents

4.3.11. Correctable Internal Error Mask Register

This register controls which errors are forwarded as Internal Correctable Errors. This register is for debug only.

Table 19.  Correctable Internal Error Mask Register (Byte Offset: 0x240)
Bits Reset Value Access Description
[31:7] 0x000 RO Reserved.
[6] 1'b0 RWS Mask for corrected internal error reported by the Application Layer.
[5] 1'b0 RWS Mask for configuration error detected in CvP mode.
[4:2] 0x0 RO Reserved.
[1] 1'b0 RWS Mask for retry buffer correctable ECC error.
[0] 1'b0 RWS Mask for RX buffer correctable ECC error.