Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

ID 683358
Date 1/02/2018
Document Table of Contents

1.5. CvP Compression and Encryption Features

Data Compression

You can choose to compress the core image by turning on the Generate compressed bitstream option in the Configuration page of the Device and Pin Options dialog box in the Quartus Prime software. The periphery image cannot be compressed. Compressing the core image reduces the storage requirement.

Data Encryption

You can choose to encrypt the core image. The periphery image cannot be encrypted. To configure the FPGA with an encrypted core image, you must pre-program the FPGA with a security key. This key is then used to decrypt the incoming configuration bitstream.

A key-programmed FPGA can accept both encrypted and unencrypted bitstreams if you configure the FPGA using the AS, PS, or FPP scheme. However, if you use CvP, a key-programmed FPGA can only accept encrypted bitstreams. Use the same key to encrypt all revisions of the core image.
Table 2.  Supported Clock Source for Encrypted Configuration DataThe following table lists the supported clock source for each conventional scheme used in a CvP system.
Key Types Active Serial Passive Serial Fast Passive Parallel
External Clock Internal Clock External Clock External Clock
Volatile key Yes Yes Yes Yes
Non-volatile key No Yes1 Yes Yes
1 The frequency value is 12.5 MHz