Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide

ID 683358
Date 1/02/2018
Document Table of Contents

3.5.3. Modifying MSEL/DIP switch on Intel® Cyclone® 10 GX Dev-Kit

The MSEL/DIP switch is labeled S1 on the back of the Intel® Cyclone® 10 GX Development Kit. The MSEL [2] is hardwired to 0. Switch the MSEL [1:0] as shown in below table.
MSEL Pin Settings for Each Configuration Scheme of Intel® Cyclone® 10 GX Devices
  • Do not drive the MSEL pins with a microprocessor or another device.
Configuration Scheme VCCPGM (V) Power-On Reset (POR) Delay Valid MSEL[2..0]
JTAG-based configuration Use any valid MSEL pin settings below
AS (x1 and x4) 1.8 Fast 010
Standard 011