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1. CvP Initialization in Intel® Cyclone® 10 GX
2. Design Considerations for CvP Initialization in Intel® Cyclone® 10 GX
3. Understanding the Design Steps for CvP Initialization in Intel® Cyclone® 10 GX
4. CvP Driver and Registers
A. Document Revision History for Intel® Cyclone® 10 GX CvP Initialization over PCI Express User Guide
4.3.1. Intel® -defined Vendor Specific Capability Header Register
4.3.2. Intel® -defined Vendor Specific Header Register
4.3.3. Intel® Marker Register
4.3.4. CvP Status Register
4.3.5. CvP Mode Control Register
4.3.6. CvP Data Registers
4.3.7. CvP Programming Control Register
4.3.8. Uncorrectable Internal Error Status Register
4.3.9. Uncorrectable Internal Error Mask Register
4.3.10. Correctable Internal Error Status Register
4.3.11. Correctable Internal Error Mask Register
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4.3.10. Correctable Internal Error Status Register
This register reports the status of the internally checked errors that are correctable. When these specific errors are enabled by the Correctable Internal Error Mask register, they are forwarded as Correctable Internal Errors as defined in the PCI Express Base Specification 3.0. This register is for debug only. Use this register to observe behavior, not to drive custom logic.
Bits | Reset Value | Access | Description |
---|---|---|---|
[31:7] | 0x000 | RO | Reserved. |
[6] | 1'b0 | RW1CS | A value of 1 indicates that the Application Layer has detected a correctable internal error. |
[5] | 1'b0 | RW1CS | A value of 1 indicates a configuration error has been detected in CvP mode, which is reported as correctable. This bit is set whenever a CVP_CONFIG_ERROR occurs while in CVP_MODE. |
[4:2] | 0x0 | RO | Reserved. |
[1] | 1'b0 | RW1CS | A value of 1 indicates a retry buffer correctable ECC error. |
[0] | 1'b0 | RW1CS | A value of 1 indicates an RX buffer correctable ECC error. |