Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 4/01/2024
Document Table of Contents

C. Cyclone® V Restrictions

Using the Intel® HLS Compiler Pro Edition to compile designs that target the Cyclone® V device family is subject to a number of restrictions.

  • Cyclone® V device support requires Quartus® Prime Standard Edition (or Lite Edition). For details, see Intel HLS Compiler Pro Edition Getting Started Guide .
  • Cyclone® V devices do not have hardened floating-point DSP blocks. Designs that target Cyclone® V devices use soft-logic for DSP functions such as multiplication, addition, or square root.
    The Intel® HLS Compiler Pro Edition cannot infer hardened floating-point dot products for Cyclone® V devices, but the compiler can rearrange operations to improve latency if you specify one or both of the following i++ command options:
    • -ffp-reassociate
    • -ffp-contract=fast