Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 4/01/2024
Document Table of Contents RTL Module Restrictions and Limitations for HLS Libraries

RTL modules that you want to include in an HLS library are subject to some restrictions and limitations to ensure that the library works consistently across different user designs.

RTL Module Restrictions

When you create an RTL module, ensure that it operates within the following restrictions:

  • The RTL module must work correctly at any clock frequency that passes timing analysis.
  • Data input and output sizes must match the sizes of the arguments and return value declared in the RTL module function signature (.h) file.

    For example, if you work with 24-bit values inside an RTL module, declare inputs to be 32 bits and declare the function signature to accept the uint data type. In the RTL module, accept the 32-bit input but discard the top 8 bits.

  • RTL modules cannot connect to external I/O signals. All input and output signals must come from the HLS component that uses the library.
  • An RTL module must have a clock port, a resetn port, and handshaking ports to support the data input and output interfaces. The handshake signal must be named ivalid, ovalid, iready, and oready.
  • Every function call that corresponds to an RTL module instantiation is completely independent of other instantiations. No hardware is shared.
  • An RTL module must receive all its inputs at the same time. A single ivalid input signifies that all inputs contain valid data.

RTL-Based Object Limitations

Using RTL modules in HLS libraries has the following limitations:

  • You can only set RTL module parameters in the object manifest file (.xml) file.

    To use the same module with multiple parameter combinations, create a separate FUNCTION tag for each parameter combination.

  • Pass data inputs to the RTL module only by value through the HLS component code.

    You cannot pass streams, pointers, or references as input to an RTL module.

    For streaming data, extract data from the stream first in your component and then pass the extracted scalar data to the RTL module in the HLS library.

    Passing data inputs to an RTL module as pointers or references causes a fatal error in the Intel® HLS Compiler.

  • Names of RTL module source files cannot conflict with the names of objects in other libraries or in file names of Intel® HLS Compiler IP.

    When you create a library, choose RTL module names that are unlike to conflict with other libraries or compiler IP. For example, prefix the name of your RTL modules with the name of your library.

    If there is a naming conflict, the Quartus® Prime compilation of the HLS component might fail or result in a functionally-incorrect FPGA image.

  • Names of the RTL module and its signals cannot conflict with reserved names defined by any of the supported RTL languages: Verilog, System Verilog, and VHDL.
  • The Intel® HLS Compiler does not support .qip files. You must manually parse nested .qip files to create a flat list of RTL files.