Intel® High Level Synthesis Compiler Pro Edition: Reference Manual
ID
683349
Date
1/23/2025
Public
1. Discontinuation of the Intel® HLS Compiler
2. Intel® HLS Compiler Pro Edition Reference Manual
3. Compiler
4. C Language and Library Support
5. Component Interfaces
6. Component Memories (Memory Attributes)
7. Loops in Components
8. Component Concurrency
9. Arbitrary Precision Math Support
10. Component Target Frequency
11. Systems of Tasks
12. Libraries
13. Advanced Hardware Synthesis Controls
14. Intel® High Level Synthesis Compiler Pro Edition Reference Summary
A. Advanced Math Source Code Libraries
B. Supported Math Functions
C. Cyclone® V Restrictions
D. Intel® HLS Compiler Pro Edition Reference Manual Archives
E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual
15. Discontinuation of the Intel® HLS Compiler
7.1. Loop Initiation Interval (ii Pragma)
7.2. Loop-Carried Dependencies (ivdep Pragma)
7.3. Loop Coalescing (loop_coalesce Pragma)
7.4. Loop Unrolling (unroll Pragma)
7.5. Loop Concurrency (max_concurrency Pragma)
7.6. Loop Iteration Speculation (speculated_iterations Pragma)
7.7. Loop Pipelining Control (disable_loop_pipelining Pragma)
7.8. Loop Interleaving Control (max_interleaving Pragma)
7.9. Loop Fusion
12.4.1.1. Integration of an RTL Module into the HLS Pipeline
12.4.1.2. RTL Module Interfaces
12.4.1.3. RTL Reset and Clock Signals
12.4.1.4. Object Manifest File Syntax
12.4.1.5. Mapping HLS Data Types to RTL Signals
12.4.1.6. HLS Emulation Models for RTL-Based Functions
12.4.1.7. Potential Incompatibility between RTL Modules and Partial Reconfiguration
12.4.1.8. Stall-Free RTL
12.4.1.9. RTL Module Restrictions and Limitations for HLS Libraries
14.1. Intel® HLS Compiler Pro Edition i++ Command-Line Arguments
14.2. Intel® HLS Compiler Pro Edition Header Files
14.3. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
14.4. Intel® HLS Compiler Pro Edition Keywords
14.5. Intel® HLS Compiler Pro Edition Simulation API (Testbench Only)
14.6. Intel® HLS Compiler Pro Edition Component Memory Attributes
14.7. Intel® HLS Compiler Pro Edition Loop Pragmas
14.8. Intel® HLS Compiler Pro Edition Scope Pragmas
14.9. Intel® HLS Compiler Pro Edition Component Attributes
14.10. Intel® HLS Compiler Pro Edition Component Default Interfaces
14.11. Intel® HLS Compiler Pro Edition Component Invocation Interface Control Attributes
14.12. Intel® HLS Compiler Pro Edition Component Macros
14.13. Intel® HLS Compiler Pro Edition Systems of Tasks API
14.14. Intel® HLS Compiler Pro Edition Pipes API
14.15. Intel® HLS Compiler Pro Edition Streaming Input Interfaces
14.16. Intel® HLS Compiler Pro Edition Streaming Output Interfaces
14.17. Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces
14.18. Intel® HLS Compiler Pro Edition Load-Store Unit Control
14.19. Intel® HLS Compiler Pro Edition Arbitrary Precision Data Types
B.1. Math Functions Provided by the math.h Header File
B.2. Math Functions Provided by the extendedmath.h Header File
B.3. Math Functions Provided by the ac_fixed_math.h Header File
B.4. Math Functions Provided by the hls_float.h Header File
B.5. Math Functions Provided by the hls_float_math.h Header File
B.6. Default Rounding Schemes and Subnormal Number Support
14.18. Intel® HLS Compiler Pro Edition Load-Store Unit Control
For variable-latency Avalon® Memory-Mapped (MM) Host interfaces (ihc::latency<0>), you can control the type of load-store unit (LSU) with the ihc::lsu template object and the corresponding load() and store() functions.
Template Object/Parameter/Function |
Description |
---|---|
ihc::lsu | The underlying LSU class template object |
ihc::style | Specifies the type of load-store unit. |
ihc::static_coalescing | Explicitly allows or prevents static coalescing of a load/store operation with other load/store operations. |
load | Loads data from memory into the LSU. |
store | Stores data from the LSU into memory. |
ihc::lsu Template Object
- Syntax
- ihc::lsu<template arguments >
- Valid Values
- N/A.
- Default Value
- N/A.
- Description
-
The underlying LSU class object.
To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/lsu_control
ihc::style Template Parameter
- Syntax
- ihc::style<LSU_type >
- Valid Values
- LSU_type can be one of the following values:
- BURST_COALESCED
- PIPELINED
- Default Value
- BURST_COALESCED
- Description
-
Specifies the type of load-store unit to create.
A burst-coalesced LSU buffers requests until the largest possible burst can be made.
A pipelined LSU submits requests as they are received.
ihc::static_coalescing Template Parameter
- Syntax
- ihc::static_coalescing<value >
- Valid Values
- true or false
- Default Value
- true
- Description
- Specifies whether to allow or prevent static coalescing of the load/store operation with other load/store operations.
load Function
- Syntax
- load(<memory_location>)
- Parameters
- The <memory_location> argument specifies the memory location to load data into the LSU from.
- Return Type
- Object of same type as the base type of the argument specified for <memory_location>.
- Description
- The load function loads data from a memory location specified by the <memory_location> argument and returns the data that the argument points to.
store Function
- Syntax
- store(<memory_location>, <value_to_store>)
- Parameters
-
The <memory_location> argument specifies the memory location to store data coming from the LSU.
The <value_to_store> argument is the value from the LSU to store in memory. The type is the same a the pointer base type.
- Return Type
- None.
- Description
- The store function stores data in the LSU to a memory location specified by the <memory_location> argument.