Intel® High Level Synthesis Compiler Pro Edition: Reference Manual
ID
683349
Date
1/23/2025
Public
1. Discontinuation of the Intel® HLS Compiler
2. Intel® HLS Compiler Pro Edition Reference Manual
3. Compiler
4. C Language and Library Support
5. Component Interfaces
6. Component Memories (Memory Attributes)
7. Loops in Components
8. Component Concurrency
9. Arbitrary Precision Math Support
10. Component Target Frequency
11. Systems of Tasks
12. Libraries
13. Advanced Hardware Synthesis Controls
14. Intel® High Level Synthesis Compiler Pro Edition Reference Summary
A. Advanced Math Source Code Libraries
B. Supported Math Functions
C. Cyclone® V Restrictions
D. Intel® HLS Compiler Pro Edition Reference Manual Archives
E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual
15. Discontinuation of the Intel® HLS Compiler
7.1. Loop Initiation Interval (ii Pragma)
7.2. Loop-Carried Dependencies (ivdep Pragma)
7.3. Loop Coalescing (loop_coalesce Pragma)
7.4. Loop Unrolling (unroll Pragma)
7.5. Loop Concurrency (max_concurrency Pragma)
7.6. Loop Iteration Speculation (speculated_iterations Pragma)
7.7. Loop Pipelining Control (disable_loop_pipelining Pragma)
7.8. Loop Interleaving Control (max_interleaving Pragma)
7.9. Loop Fusion
12.4.1.1. Integration of an RTL Module into the HLS Pipeline
12.4.1.2. RTL Module Interfaces
12.4.1.3. RTL Reset and Clock Signals
12.4.1.4. Object Manifest File Syntax
12.4.1.5. Mapping HLS Data Types to RTL Signals
12.4.1.6. HLS Emulation Models for RTL-Based Functions
12.4.1.7. Potential Incompatibility between RTL Modules and Partial Reconfiguration
12.4.1.8. Stall-Free RTL
12.4.1.9. RTL Module Restrictions and Limitations for HLS Libraries
14.1. Intel® HLS Compiler Pro Edition i++ Command-Line Arguments
14.2. Intel® HLS Compiler Pro Edition Header Files
14.3. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
14.4. Intel® HLS Compiler Pro Edition Keywords
14.5. Intel® HLS Compiler Pro Edition Simulation API (Testbench Only)
14.6. Intel® HLS Compiler Pro Edition Component Memory Attributes
14.7. Intel® HLS Compiler Pro Edition Loop Pragmas
14.8. Intel® HLS Compiler Pro Edition Scope Pragmas
14.9. Intel® HLS Compiler Pro Edition Component Attributes
14.10. Intel® HLS Compiler Pro Edition Component Default Interfaces
14.11. Intel® HLS Compiler Pro Edition Component Invocation Interface Control Attributes
14.12. Intel® HLS Compiler Pro Edition Component Macros
14.13. Intel® HLS Compiler Pro Edition Systems of Tasks API
14.14. Intel® HLS Compiler Pro Edition Pipes API
14.15. Intel® HLS Compiler Pro Edition Streaming Input Interfaces
14.16. Intel® HLS Compiler Pro Edition Streaming Output Interfaces
14.17. Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces
14.18. Intel® HLS Compiler Pro Edition Load-Store Unit Control
14.19. Intel® HLS Compiler Pro Edition Arbitrary Precision Data Types
B.1. Math Functions Provided by the math.h Header File
B.2. Math Functions Provided by the extendedmath.h Header File
B.3. Math Functions Provided by the ac_fixed_math.h Header File
B.4. Math Functions Provided by the hls_float.h Header File
B.5. Math Functions Provided by the hls_float_math.h Header File
B.6. Default Rounding Schemes and Subnormal Number Support
7.3. Loop Coalescing (loop_coalesce Pragma)
Use the loop_coalesce pragma to direct the Intel® HLS Compiler to coalesce nested loops into a single loop without affecting the loop functionality. Coalescing loops can help reduce your component area usage by directing the compiler to reduce the overhead needed for loop control.
Coalescing nested loops also reduces the latency of the components, which can further reduce your component area usage. However, in some cases, coalescing loops might lengthen the critical loop initiation interval path, so coalescing loops might not be suitable for all components.
To coalesce nested loops, specify the pragma as follows:
#pragma loop_coalesce <loop_nesting_level>
The <loop_nesting_level> parameter is optional and is an integer that specifies how many nested loop levels that you want the compiler to attempt to coalesce. If you do not specify the <loop_nesting_level> parameter, the compiler attempts to coalesce all of the nested loops.
For example, consider the following set of nested loops:
If you place the pragma before loop (A), then the loop nesting level for these loops is defined as:
for (A) for (B) for (C) for (D) for (E)
- Loop (A) has a loop nesting level of 1.
- Loop (B) has a loop nesting level of 2.
- Loop (C) has a loop nesting level of 3.
- Loop (D) has a loop nesting level of 4.
- Loop (E) has a loop nesting level of 3.
Depending on the loop nesting level that you specify, the compiler attempts to coalesce loops differently:
- If you specify #pragma loop_coalesce 1 on loop (A), the compiler does not attempt to coalesce any of the nested loops.
- If you specify #pragma loop_coalesce 2 on loop (A), the compiler attempts to coalesce loops (A) and (B).
- If you specify #pragma loop_coalesce 3 on loop (A), the compiler attempts to coalesce loops (A), (B), (C), and (E).
- If you specify #pragma loop_coalesce 4 on loop (A), the compiler attempts to coalesce all of the loops [loop (A) - loop (E)].
To learn more about the effects of applying the loop_coalesce loop pragma, review the following tutorial:
<quartus_installdir>/hls/examples/tutorials/best_practices/loop_coalesce
Example
The following simple example shows how the compiler coalesces two loops into a single loop.
Consider a simple nested loop written as follows:
The compiler coalesces the two loops together so that they run as if they were a single loop written as follows:
#pragma loop_coalesce for (int i = 0; i < N; i++) for (int j = 0; j < M; j++) sum[i][j] += i+j;
int i = 0; int j = 0; while(i < N){ sum[i][j] += i+j; j++; if (j == M){ j = 0; i++; } }