Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

Download PDF
ID 683349
Date 1/23/2025
Public
Document Table of Contents
Document Table of Contents x
1. Discontinuation of the Intel® HLS Compiler 2. Intel® HLS Compiler Pro Edition Reference Manual 3. Compiler 4. C Language and Library Support 5. Component Interfaces 6. Component Memories (Memory Attributes) 7. Loops in Components 8. Component Concurrency 9. Arbitrary Precision Math Support 10. Component Target Frequency 11. Systems of Tasks 12. Libraries 13. Advanced Hardware Synthesis Controls 14. Intel® High Level Synthesis Compiler Pro Edition Reference Summary A. Advanced Math Source Code Libraries B. Supported Math Functions C. Cyclone® V Restrictions D. Intel® HLS Compiler Pro Edition Reference Manual Archives E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual 15. Discontinuation of the Intel® HLS Compiler
3. Compiler x
3.1. Intel® HLS Compiler Pro Edition Command Options 3.2. Using Libraries in Your Component 3.3. Compiler Interoperability 3.4. Intel® HLS Compiler Hardware Model
3.3. Compiler Interoperability x
3.3.1. Compiling Your Testbench and Component Separately
4. C Language and Library Support x
4.1. Supported C and C++ Subset for Component Synthesis 4.2. C and C++ Libraries 4.3. Templated and Overloaded Functions 4.4. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
4.3. Templated and Overloaded Functions x
4.3.1. Templated Functions 4.3.2. Overloaded Functions 4.3.3. Function Name Mapping
5. Component Interfaces x
5.1. Component Invocation Interface 5.2. Avalon® Streaming Interfaces 5.3. Pipes 5.4. Avalon® Memory-Mapped Host Interfaces 5.5. Agent Interfaces 5.6. Stable Component Parameters 5.7. Global Variables 5.8. Structs in Component Interfaces 5.9. Reset Behavior
5.1. Component Invocation Interface x
5.1.1. Scalar Parameters 5.1.2. Pointer and Reference Parameters 5.1.3. Interface Definition Example: Component Invocation Interface Control Attributes 5.1.4. Interface Definition Example: Component with Both Scalar and Pointer Arguments
5.3. Pipes x
5.3.1. The pipe Class and Its Use
5.4. Avalon® Memory-Mapped Host Interfaces x
5.4.1. Memory-Mapped Host Testbench Constructor 5.4.2. Implicit and Explicit Examples of Describing a Memory Interface 5.4.3. Avalon® Memory-Mapped Host Interfaces and Load-Store Units
5.4.3. Avalon® Memory-Mapped Host Interfaces and Load-Store Units x
5.4.3.1. Load-Store Unit Types 5.4.3.2. Memory-Access Coalescing and Load-Store Units
5.5. Agent Interfaces x
5.5.1. Control and Status Register (CSR) Agent 5.5.2. Agent Memories
6. Component Memories (Memory Attributes) x
6.1. Static Variables
7. Loops in Components x
7.1. Loop Initiation Interval (ii Pragma) 7.2. Loop-Carried Dependencies (ivdep Pragma) 7.3. Loop Coalescing (loop_coalesce Pragma) 7.4. Loop Unrolling (unroll Pragma) 7.5. Loop Concurrency (max_concurrency Pragma) 7.6. Loop Iteration Speculation (speculated_iterations Pragma) 7.7. Loop Pipelining Control (disable_loop_pipelining Pragma) 7.8. Loop Interleaving Control (max_interleaving Pragma) 7.9. Loop Fusion
7.9. Loop Fusion x
7.9.1. Loop Fusion Control (loop_fuse Pragma) 7.9.2. Loop Fusion Exemption (nofusion pragma)
8. Component Concurrency x
8.1. Serial Equivalence within a Memory Space or I/O 8.2. Concurrency Control (hls_max_concurrency Attribute) 8.3. Component Pipelining Control (hls_disable_component_pipelining Attribute)
9. Arbitrary Precision Math Support x
9.1. Declaring ac_int Data Types 9.2. Declaring ac_fixed Data Types 9.3. Declaring ac_complex Data Types 9.4. AC Data Types and Native Compilers 9.5. Declaring hls_float Data Types
9.1. Declaring ac_int Data Types x
9.1.1. Important Usage Information on the ac_int Data Type 9.1.2. Integer Promotion and ac_int Data Types 9.1.3. Debugging Your Use of the ac_int Data Type
9.2. Declaring ac_fixed Data Types x
9.2.1. Arbitrary Precision Fixed-Point Literals in Operations
9.5. Declaring hls_float Data Types x
9.5.1. Operators and Return Types Supported by the hls_float Data Type 9.5.2. Additional Data Types Provided By hls_float.h
10. Component Target Frequency x
10.1. Effects of Specifying Target II and Target fMAX
11. Systems of Tasks x
11.1. Task Functions 11.2. Internal Streams 11.3. System of Tasks Simulation
12. Libraries x
12.1. Static-Object Libraries 12.2. Creating a Static-Object Library 12.3. Creating Objects From HLS Code 12.4. Creating Objects From RTL Code 12.5. Packaging Object Files Into a Library
12.3. Creating Objects From HLS Code x
12.3.1. Creating an Object File From HLS Code 12.3.2. Supported OpenCL™ Language Constructs
12.4. Creating Objects From RTL Code x
12.4.1. RTL Modules and the HLS Pipeline 12.4.2. Creating a Static-Object File from an RTL Module
12.4.1. RTL Modules and the HLS Pipeline x
12.4.1.1. Integration of an RTL Module into the HLS Pipeline 12.4.1.2. RTL Module Interfaces 12.4.1.3. RTL Reset and Clock Signals 12.4.1.4. Object Manifest File Syntax 12.4.1.5. Mapping HLS Data Types to RTL Signals 12.4.1.6. HLS Emulation Models for RTL-Based Functions 12.4.1.7. Potential Incompatibility between RTL Modules and Partial Reconfiguration 12.4.1.8. Stall-Free RTL 12.4.1.9. RTL Module Restrictions and Limitations for HLS Libraries
12.4.1.2. RTL Module Interfaces x
12.4.1.2.1. RTL Module Interface Signals
12.4.1.3. RTL Reset and Clock Signals x
12.4.1.3.1. Intel Agilex® 7 and Stratix® 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules
12.4.1.4. Object Manifest File Syntax x
12.4.1.4.1. XML Elements for ATTRIBUTES 12.4.1.4.2. XML Elements for INTERFACE 12.4.1.4.3. XML Elements for RESOURCES
12.4.1.4.1. XML Elements for ATTRIBUTES x
12.4.1.4.1.1. Interaction Between ALLOW_MERGINGand HAS_SIDE_EFFECTS Elements
13. Advanced Hardware Synthesis Controls x
13.1. Hardware Implementation Control for Math Functions 13.2. The hls_fpga_reg() Function
13.1. Hardware Implementation Control for Math Functions x
13.1.1. Math Function Hardware Implementation Summary 13.1.2. The --dsp-mode Command Option 13.1.3. The ihc::math_dsp_control Function
14. Intel® High Level Synthesis Compiler Pro Edition Reference Summary x
14.1. Intel® HLS Compiler Pro Edition i++ Command-Line Arguments 14.2. Intel® HLS Compiler Pro Edition Header Files 14.3. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros 14.4. Intel® HLS Compiler Pro Edition Keywords 14.5. Intel® HLS Compiler Pro Edition Simulation API (Testbench Only) 14.6. Intel® HLS Compiler Pro Edition Component Memory Attributes 14.7. Intel® HLS Compiler Pro Edition Loop Pragmas 14.8. Intel® HLS Compiler Pro Edition Scope Pragmas 14.9. Intel® HLS Compiler Pro Edition Component Attributes 14.10. Intel® HLS Compiler Pro Edition Component Default Interfaces 14.11. Intel® HLS Compiler Pro Edition Component Invocation Interface Control Attributes 14.12. Intel® HLS Compiler Pro Edition Component Macros 14.13. Intel® HLS Compiler Pro Edition Systems of Tasks API 14.14. Intel® HLS Compiler Pro Edition Pipes API 14.15. Intel® HLS Compiler Pro Edition Streaming Input Interfaces 14.16. Intel® HLS Compiler Pro Edition Streaming Output Interfaces 14.17. Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces 14.18. Intel® HLS Compiler Pro Edition Load-Store Unit Control 14.19. Intel® HLS Compiler Pro Edition Arbitrary Precision Data Types
14.13. Intel® HLS Compiler Pro Edition Systems of Tasks API x
14.13.1. ihc::stream Class
A. Advanced Math Source Code Libraries x
A.1. Random Number Generator Library A.2. Matrix Multiplication Library A.3. Cholesky Decomposition Library
B. Supported Math Functions x
B.1. Math Functions Provided by the math.h Header File B.2. Math Functions Provided by the extendedmath.h Header File B.3. Math Functions Provided by the ac_fixed_math.h Header File B.4. Math Functions Provided by the hls_float.h Header File B.5. Math Functions Provided by the hls_float_math.h Header File B.6. Default Rounding Schemes and Subnormal Number Support
1. Discontinuation of the Intel® HLS Compiler
2. Intel® HLS Compiler Pro Edition Reference Manual
3. Compiler
4. C Language and Library Support
5. Component Interfaces
6. Component Memories (Memory Attributes)
7. Loops in Components
8. Component Concurrency
9. Arbitrary Precision Math Support
10. Component Target Frequency
11. Systems of Tasks
12. Libraries
13. Advanced Hardware Synthesis Controls
14. Intel® High Level Synthesis Compiler Pro Edition Reference Summary
A. Advanced Math Source Code Libraries
B. Supported Math Functions
C. Cyclone® V Restrictions
D. Intel® HLS Compiler Pro Edition Reference Manual Archives
E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual
15. Discontinuation of the Intel® HLS Compiler

7.7. Loop Pipelining Control (disable_loop_pipelining Pragma)

When the loop iterations effectively execute sequentially due to loop-carried dependencies, use the disable_loop_pipelining pragma to generate a simple sequential datapath and avoid loop resource hardware duplication. The simpler datapath and lack of resource duplication in hardware reduces the FPGA area utilization of your component.

Use the Loop Analysis section of the high-level design reports (report.html) to help determine if you should apply this pragma to your loops.

In the following example, the Intel® HLS Compiler fails to schedule the loop with a small loop initiation interval (II) because of a memory dependency. Pipelining this loop is unlikely to have any benefit to your component throughput or performance. 
#pragma disable_loop_pipelining
for (int i = 1; i < N; i++) {
    int j = a[i-1];
    // Memory dependency induces a high-latency loop feedback path
    a[i] = foo(j)
}

You can also disable pipelining the datapath of your entire component with the hls_disable_component_pipelining component attribute. For more information about this attribute, see Component Pipelining Control (hls_disable_component_pipelining Attribute).

Level Two Title