2.5. Simulating the 100G Interlaken IP Core
You can simulate your 100G Interlaken IP core variation using any of the vendor-specific IEEE encrypted functional simulation models which are generated in the new <instance name>_sim or <instance name>/sim subdirectory of your project directory.
The 100G Interlaken IP core supports the VCS* , Xcelium* , QuestaSim* , and ModelSim* SE simulators.
The 100G Interlaken IP core generates only a Verilog HDL simulation model and testbench. The IP core parameter editor appears to offer you the option of generating a VHDL simulation model, but this IP core does not support a VHDL simulation model or testbench.
For more information about functional simulation models for Intel® IP cores, refer to the Simulating Intel® Designs chapter in volume 3 of the Quartus Prime Handbook.
For non- Intel® Arria® 10 variations with Verilog HDL models, if you turn on Generate example design when you generate the IP core, the Quartus Prime software generates a testbench. This testbench demonstrates the resetting, clocking, and toggling of the 100G Interlaken IP core user interfaces in simulation. For Intel® Arria® 10 variations, you can generate both this testbench and a hardware example design by clicking Generate Example Design in the 100G Interlaken parameter editor.
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