100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 10/31/2022
Document Table of Contents

1.1. Features

The 100G Interlaken IP core has the following features:

  • Compliant with the Interlaken Protocol Specification, Revision 1.2.
  • Supports 12 and 24 serial lanes in configurations that provide up to 150  Gbps raw bandwidth.
  • Supports per‑lane data rates of 6.25, 10.3125, and 12.5 Gbps using Intel® on‑chip high‑speed transceivers.
  • Supports dynamically configurable BurstMax and BurstMin values.
  • Supports Packet mode and Interleaved (Segmented) mode for user data transfer.
  • Supports dual segment mode for efficient user data transfer.
  • Supports up to 256 logical channels in out‑of‑the‑box configuration.
  • Supports optional user‑controlled in‑band flow control with 1, 2, 4, 8, or 16 16‑bit calendar pages.
  • Supports optional out‑of‑band flow control blocks.
  • Supports memory block ECC in Stratix V and Intel® Arria® 10 devices.