A. Performance and Fmax Requirements for 100G Ethernet Traffic
To achieve 100G Ethernet line rates through the application interface of your 100G Interlaken IP core, you must run the transmit side and receiver side user interface clocks tx_usr_clk and rx_usr_clk at the following minimum required operating frequency:
- 300 MHz in single segment mode and in 24 lane variations2
- 225 MHz in 12 lane variations in dual segment mode
The following discussion describes the packet rate calculation that supports this requirement.
To transmit a minimum size (64-byte) Ethernet packet, the Interlaken link transmitter must send 672 bits of data.
To support an Ethernet line rate of 100Gb/s , the Interlaken link must process 1000 bits in 10ns. The following calculation derives the required clock frequency.
This packet rate requires that the user interface handle one packet per cycle if the operating clock runs at 150 MHz, or one packet per two cycles if the operating clock runs at 300 MHz.
In dual segment mode, because the final cycle of one packet can overlap with the initial cycle of another packet, the operating clock frequency requirements are derived from the average number of cycles required for a single packet in back-to-back traffic. The calculations that follow show that the minimum operating clock frequency in dual segment mode is 225 MHz.
The following figures explain the derivation of the minimum frequency requirements.
A 65-byte packet comprises (65 + 20) x 8 = 680 bits. Therefore, for traffic that consists mainly of 65-byte packets, the most inefficient traffic possible, the user interface must handle:
100 x 1,000,000,000 bits/sec ÷ 680 = 147 Million packets/sec, or one packet every 6.8 ns.
Case 2 in the single segment mode figure shows that the user interface requires two cycles to process each 65-byte packet. At 300 MHz, two cycles take 6.66 ns, which is a sufficiently small amount of time.
A 129-byte packet comprises (129 + 20) x 8 = 1192 bits. Therefore, for traffic that consists mainly of 129-byte packets, the user interface must handle:
100 x 1,000,000,000 bits/sec ÷ 1192 = 83.9 Million packets/sec, or one packet every 11.9 ns.
Case 3 in the single segment mode figure shows that the user interface requires three cycles to process each 129-byte packet. At 300 MHz, three cycles take 10 ns, which is a sufficiently small amount of time.
The same calculations applied to lower frequencies yield an average time per packet that is not sufficiently short. Therefore, 300 MHz is the recommended frequency for the two user data transfer interface clocks in your single segment mode 100G Interlaken IP core. For logistical clocking reasons, this frequency is also recommended for your 24-lane variation in dual segment mode.
In dual segment mode, a 65-byte packet or a 129-byte packet can be followed in the same cycle by the first 32 bytes of the following packet. The table summarizes the numbers illustrated in the figure.
|Packet Size (Bytes)||Processing Time||Required Maximum Time per Packet (ns) (derived earlier)|
|Number of Cycles for Two Consecutive Packets||At 225 MHz:|
|Time for Two Consecutive Packets (ns)||Average Time per Packet (ns)|
Both of the average times per packet are sufficiently short, based on the packets per second requirements for the different sized packets (6.66 < 6.8 and 11.12 < 11.9). The same calculations applied to lower frequencies yield an average time per packet that is not sufficiently short. Therefore, 225 MHz is the recommended frequency for the two user data transfer interface clocks in your 12-lane, dual segment mode 100G Interlaken IP core.
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