100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 10/31/2022
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8.1.2. RXFIFO Address Width

The RXFIFO Address Width parameter specifies the number of bits in the address (offset) of an entry in the RX Reassembly FIFO. The number of bits is log2 of the depth of this FIFO. Each RX Reassembly FIFO entry is a 64-bit word.

The default value for the RXFIFO Address Width parameter is 12, specifying this FIFO can hold 212 (==4K) 64-bit words. Adjusting this parameter may affect your ability to close timing for your design. However, you can adjust this parameter subject to the successful closure of the timing.