1. About This IP Core
2. Getting Started With the 100G Interlaken IP Core
3. 100G Interlaken IP Core Parameter Settings
4. Functional Description
5. 100G Interlaken IP core Signals
6. 100G Interlaken IP Core Register Map
7. 100G Interlaken IP Core Test Features
8. Advanced Parameter Settings
9. Out-of-Band Flow Control in the 100G Interlaken IP core
10. 100G Interlaken Intel® FPGA IP User Guide Archives
11. Document Revision History for 100G Interlaken Intel® FPGA IP User Guide
A. Performance and Fmax Requirements for 100G Ethernet Traffic
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Specifying the 100G Interlaken IP Core Parameters and Options
2.3. Files Generated for Arria V GZ and Stratix V Variations
2.4. Files Generated for Intel® Arria® 10 Variations
2.5. Simulating the 100G Interlaken IP Core
2.6. Integrating Your IP Core in Your Design
2.7. Compiling the Full Design and Programming the FPGA
2.8. Creating a Signal Tap Debug File to Match Your Design Hierarchy
3.1. Number of Lanes
3.2. Meta Frame Length in Words
3.3. Data Rate
3.4. Transceiver Reference Clock Frequency
3.5. Include Advanced Error Reporting and Handling
3.6. Enable M20K ECC Support
3.7. Include Diagnostic Features
3.8. Enable Native PHY Debug Master Endpoint (NPDME)
3.9. Include In-Band Flow Control Block
3.10. Number of Calendar Pages
3.11. TX Scrambler Seed
3.12. Transfer Mode Selection
3.13. Data Format
5.1. 100G Interlaken IP Core Clock Interface Signals
5.2. 100G Interlaken IP Core Reset Interface Signals
5.3. 100G Interlaken IP Core User Data Transfer Interface Signals
5.4. 100G Interlaken IP Core Interlaken Link and Miscellaneous Interface Signals
5.5. 100G Interlaken IP Core Management Interface
5.6. Device Dependent Signals
8.1.3. SWAP_TX_LANES and SWAP_RX_LANES (Data Word Lane Swapping)
The 100G Interlaken IP core supports a lane reversal feature (lane swapping). Lane swapping parameters determine the order in which blocks are distributed and gathered from the lanes. The 100G Interlaken IP core provides the following two options for the lane order:
- Straight Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with the top lane, ending with Lane 0. The receiver takes in Interlaken blocks starting with the top lane, ending with Lane 0.
Figure 23. Straight Lane Order
- Swapped Lane order. The transmitter sends Interlaken blocks sequentially across the lanes starting with Lane 0, ending with Lane N. The receiver takes in Interlaken blocks starting with Lane 0, ending with Lane N.
Figure 24. Swapped Lane Order
Two parameters determine lane order:
SWAP_TX_LANES
SWAP_RX_LANES
When a parameter is set to 0, the 100G Interlaken IP core implements the Straight Lane order. When a parameter is set to 1, the 100G Interlaken IP core implements the Swapped Lane order. The TX and RX parameters are independent and can be set separately.
To conform with the Interlaken specification, the default value of SWAP_TX_LANES and SWAP_RX_LANES is 1.
Note: Running traffic with incompatible lane swapping configuration results in CRC24 errors and incorrect data at the receiver.
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