100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 10/31/2022
Document Table of Contents

7.2. External Loopback Mode

The 100G Interlaken IP core operates correctly in an external loopback configuration.

To put the IP core in external loopback mode, connect the TX lanes to the RX lanes of the IP core. This mode does not require any special programming of the IP core.