7.4. CRC32 Error Injection
The 100G Interlaken IP core supports the injection of CRC32 errors on the Interlaken link for validation of the Interlaken link partner's error handling, and for validation of this IP core's error handling in a loopback configuration. Variations that target an Arria V or Stratix V device require that you first enable the feature in the hard PCS; variations that target an Intel® Arria® 10 device do not require this step.
This feature is available if you turn on Include diagnostic features in the 100G Interlaken parameter editor.
To enable the CRC32 error injection feature in your 100G Interlaken IP core that targets an Arria V or Stratix V device, set the value of bit  of the hard PCS register at offset 0x138 (offset 0xC from the hard PCS base address of 0x12C) to the value of 1. Ensure you set the register bit using a read-modify-write register access sequence, to avoid modifying the other register fields. This step is not necessary in 100G Interlaken IP core devices that target an Intel® Arria® 10 device, because CRC32 error injection is enabled by default in these variations.
For instructions to program the hard PCS registers in Arria V and Stratix V devices, refer to the Native PHY IP Core chapter for your target device family and to the Transceiver Reconfiguration Controller chapter of the Intel® Transceiver PHY IP Core User Guide.
After you enable the IP core to inject CRC32 errors in the output to the Interlaken link, you can turn on the feature using the 100G Interlaken IP core CRC32_ERR_INJECT register. You must maintain each register bit at the value of 1 for the duration of a Meta Frame, at least, to ensure that the IP core transmits at least one CRC32 error on the corresponding lane.
After your testing is complete, in Arria V and Stratix V devices, you must reset the hard PCS register bit to its default value of zero to enable normal operation.
The 100G Interlaken IP core CRC32 error injection feature does not keep a count of the errors injected.
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