100G Interlaken Intel® FPGA IP User Guide

ID 683338
Date 10/31/2022
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7.3.2. Setting up PRBS Mode in Intel® Arria® 10 Devices

To enable the IP core to generate PRBS output, for each Interlaken lane, you must program the relevant hard PCS registers to enable the PRBS generator clock, to set the test_enable bit, and to select the PRBS polynomial. To enable the IP core to receive PRBS input, for each Interlaken lane, you must program the relevant hard PCS registers to enable the PRBS receiver clock and to select the expected PRBS polynomial, in addition to some bookkeeping tasks. If you perform your PRBS testing in loopback mode, you must enable the IP core to both generate and receive PRBS sequences. After you set the hard PCS registers for PRBS mode, you must perform a soft reset of the transceiver.

The PRBS feature is available only if you turn on Include diagnostic features in the 100G Interlaken parameter editor.

This section describes the register values you must program. For instructions to program the registers that activate the PRBS test feature in your Intel® Arria® 10 100G Interlaken IP core, refer to the hard PCS register information in the Intel® Arria® 10 Transceiver PHY User Guide. You program the hard PCS registers using the 100G Interlaken IP core Intel® Arria® 10 transceiver reconfiguration interface.

Table 27.  Programming the Hard PCS Registers in Intel® Arria® 10 Devices

To turn on the PRBS feature in the hard PCS for IP core variations that target an Intel® Arria® 10 device, you must program the following hard PCS registers in the order shown, for each of the TX and RX sides. These registers are not accessible using the 100G Interlaken IP core management interface. You must access these registers through the Arria 10 transceiver reconfiguration interface of the 100G Interlaken IP core.

Ensure you set these register bits using a read-modify-write register access sequence (per register), to avoid modifying the other register fields.

TX Register Offset Bits Meaning Action
1 0x6 [2:0] TX test enable Set this field to the value of 3'b100 to enable the PRBS pattern generator in the transmitter.
[3] PRBS width select Set this bit to the value of 0 to specify that the PRBS width is 64 bits.
[7:6] Enable TX PRBS clock Set this field to the value of 2'b01 to enable the TX PRBS clock.
2 0x7 [2] Invert TX channels Set this bit to the value of 0 to specify that the outgoing PRBS be inverted, or set this bit to the value of 1 to specify that the outgoing PRBS not be inverted. The default value of this register field is 0. By default, the outgoing PRBS is inverted.
[5] Enable PRBS9 Set one of these bits to the value of 1, and the others to the value of 0, to select the TX polynomial.
[6] Enable PRBS15
[7] Enable PRBS23
3 0x8 [4] Enable PRBS31
RX Register Offset Bits Meaning Action
1 0xA [4] Invert RX channels Set this bit to the value of 0 to specify that the PCS should expect the incoming PRBS to be inverted, or set this bit to the value of 1 to specify that the PCS should not expect the incoming PRBS to be inverted. The default value of this bit is 0. In loopback mode, you should set this bit to match the setting in the PRBS transmitter.
[7] Enable RX PRBS clock Set this bit to the value of 1 to enable the RX PRBS clock.
2 0xB [1] Enable 10G PCS mode Set this bit to the value of 1 to specify the PCS is in 10G PCS mode.
[3:2] Verifier counter threshold Set this field to the value your design requires to ensure adequate lead time before the PRBS checker begins counting PRBS errors. The field value specifies the wait time in number of clk_rx_common clock cycles. A counter begins counting clk_rx_common clock cycles after the soft reset, and triggers the start of PRBS checking when the specified threshold is reached. This field has the following valid values:
  • 2'b00—Specifies the counter threshold (the wait time) is 127.
  • 2'b01—Specifies the counter threshold is 255.
  • 2'b10—Specifies the counter threshold is 511.
  • 2'b11—Specifies the counter threshold is 1023.
[5] Enable PRBS9 Set one of these bits to the value of 1, and the others to the value of 0, to select the expected polynomial.
[6] Enable PRBS15
[7] Enable PRBS23
3 0xC [0] Enable PRBS31
[1] Confirm 10G PCS mode Set this bit to the value of 1 to confirm the PCS is in 10G mode.
[3] PRBS width select Set this bit to the value of 0 to specify that the PRBS width is 64 bits.
4 0x13F [3:0] RX Deserializer width select Set this field to the value of 4'b1110 to specify that the data width after deserialization is 64 bits.

After you enable the IP core to generate or receive PRBS output, by setting the relevant register field values for each Interlaken lane, you must perform a soft reset of the transceiver transmitters and receivers. To perform a soft reset of the transceiver transmitters and receivers, on the 100G Interlaken IP core management interface, program bit [2] of the 100G Interlaken IP core RESET register at offset 0x13 with the value of 1. On the following mm_clk cycle, or later, program the bit 0x13[2] with the value of 0 to clear the reset. After you reset the transceivers and subsequently clear the reset bit, the IP core immediately begins transmitting PRBS output on the Interlaken link. You can check the receive PRBS status in the 100G Interlaken IP core PRBS status registers (RX_PRBS_DONE, RX_PRBS_ERR, and RX_PRBS_COUNT).

After your testing is complete, you must reset these register bits to their default values and perform the soft reset to enable normal operation.