Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Public
Document Table of Contents

3.3.3. Timing for Memory Write and Read of Function 1 256-Bit Avalon-ST Interface

The following timing diagram illustrates memory to Function 1 which occurs in the simulation starting at time 99102 ns.

Figure 14. Timing for Memory Write and Read of Function 1

The timing diagram illustrates the following sequence of events:

  1. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Memory Write to Function 1, asserting its RxStSop_i and RxStValid_i signals.
  2. At the falling edge of RxStSop_i, RxmFunc1Sel_o is asserted and the write data is driven on RxmWriteData_0_o[31:0]. The Memory Write to Function 1 completes when the data is written.
  3. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Memory Read to Function 1, asserting its RxStSop_i and RxStValid_i signals.
  4. After the falling edge of RxStSop_i, the RX Avalon-MM master interface asserts RxmRead_0_o to Function 1.
  5. At the falling edge of RxmRead_0_o, Function 1 asserts RxmReadDataValid_0 and drives the data on RxmReadData_0_i[ 31:0].
  6. The host receives the completion data when TxStValid_o, TxStSop_o, and TxStEop_o are asserted.