Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Public
Document Table of Contents

4.1. System Settings

Table 12.  System Settings for PCI Express

Parameter

Value

Description

Number of Lanes

×1, ×2, ×4, ×8

Specifies the maximum number of lanes supported.

Lane Rate

Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Gen3 (2.5/5.0/8.0 Gbps) 

Specifies the maximum data rate at which the link can operate.

Port type

Native Endpoint

Root Port

Legacy Endpoint

Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility. The Legacy Endpoint is not available for the Avalon-MM Arria® V GZ Hard IP for PCI Express.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configuration Space.

PCI Express Base Specification version

2.1

3.0

Select either the 2.1 or 3.0 specification.
Application Interface Avalon-ST 64-bit

Avalon-ST 128-bit

Avalon-ST 256-bit

Specifies the width of the Avalon-ST interface. By doubling the interface width allows you to run your Application Layer at half the frequency.

RX Buffer credit allocation -performance for received requests

Minimum

Low

Balanced

High

Maximum

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KByte RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter for more information about optimizing performance. The Throughput Optimization chapter explains how the RX credit allocation and the Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation of flow control credits. You can set the Maximum payload size parameter on the Device tab.

The Message window dynamically updates the number of credits for Posted, Non-Posted Headers and Data, and Completion Headers and Data as you change this selection.

  • Minimum—configures the minimum PCIe specification allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.
  • Low—configures a slightly larger amount of RX Buffer space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.
  • Balanced—configures approximately half the RX Buffer space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.
  • High—configures most of the RX Buffer space for received requests and allocates a slightly larger than minimum amount of space for received completions. Select this option where most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic only infrequently generates a small burst of read requests. This option is recommended for typical root port applications where most of the PCIe traffic is generated by DMA engines located in the endpoints.
  • Maximum—configures the minimum PCIe specification allowed amount of completion space, leaving most of the RX Buffer space for received requests. Select this option when most of the PCIe requests are generated by the other end of the PCIe link and the local application layer logic never or only infrequently generates single read requests. This option is recommended for control and status endpoint applications that don't generate any PCIe requests of their own and only are the target of write and read requests from the root complex.

Reference clock frequency

100 MHz

125 MHz

The PCI Express Base Specification 3.0 requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source. For more information about Gen3 operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the specification.

For Gen3, Altera recommends using a common reference clock (0 ppm) because when using separate reference clocks (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causes the PCIe link to go to recovery. Arria® V GZ PCIe Hard IP in Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this is a slight decrease in bandwidth. On Gen3 x8 systems, this bandwidth impact is negligible. If non 0 ppm mode is required, so that separate reference clocks are being used, please contact Altera for further information and guidance.

Use 62.5 MHz application clock

On/Off

This mode is only available only for Gen1 ×1.

Use deprecated RX Avalon-ST data byte enable port (rx_st_be)

On/Off

This parameter is only available for the Avalon‑ST Arria® V GZ Hard IP for PCI Express.

Enable byte parity ports on Avalon-ST interface

On/Off

When On, the RX and TX datapaths are parity protected. Parity is odd.

This parameter is only available for the Avalon‑ST Arria® V GZ Hard IP for PCI Express.

Enable multiple packets per cycle

On/Off

When On, the 256‑bit Avalon‑ST interface supports the transmission of TLPs starting at any 128‑bit address boundary, allowing support for multiple packets in a single cycle. To support multiple packets per cycle, the Avalon‑ST interface includes 2 start of packet and end of packet signals for the 256‑bit Avalon‑ST interfaces. This feature is only supported for Gen3 ×8.

For more information refer to Tradeoffs of Consider when Enabling Multiple Packets per Cycle.

Enable configuration via PCIe link

On/Off

When On, the Quartus® Primesoftware places the Endpoint in the location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below. CvP is not supported for Gen3 variants.

Enable credit consumed selection port tx_cons_cred_sel

On/Off

When you turn on this option, the core includes the tx_cons_cred_sel port. This parameter does not apply to the Avalon-MM interface.

Enable Configuration Bypass

On/Off

When On, the Arria® V GZ Hard IP for PCI Express bypasses the Transaction Layer Configuration Space registers included as part of the Hard IP, allowing you to substitute a custom Configuration Space implemented in soft logic.

This parameter is not available for the Avalon‑MM IP Cores.

Enable Hard IP Reconfiguration

On/Off

When On, you can use the Hard IP reconfiguration bus to dynamically reconfigure Hard IP read‑only registers. For more information refer to Hard IP Reconfiguration Interface. This parameter is not available for the Avalon-MM IP Cores.

Enable Hard IP completion tag checking

On/Off

When enabled, the Hard IP can use 32 or 64 tags for completions and validates completion tags. When disabled, the Hard IP can use up to 256 tags. The Application Layer logic must validate completion tags.
Enable Hard IP reset pulse at power-up when using the soft reset controller

On/Off

When On, the soft reset controller generates a pulse at power up to reset the Hard IP. This pulse ensures that the Hard IP is reset after programming the device, regardless of the behavior of the dedicated PCI Express reset pin, perstn. This option is available for Gen2 and Gen3 designs that use a soft reset controller.