Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Public
Document Table of Contents

5.6. Interrupts for Root Ports

Table 29.  Interrupt Signals for Root Ports

Signal

Direction

Description

int_status[3:0]

Output

These signals drive legacy interrupts to the Application Layer as follows:

  • int_status[0]: interrupt signal A
  • int_status[1]: interrupt signal B
  • int_status[2]: interrupt signal C
  • int_status[3]: interrupt signal D
serr_out

Output

System Error: This signal only applies to Root Port designs that report each system error detected, assuming the proper enabling bits are asserted in the Root Control and Device Control registers. If enabled, serr_out is asserted for a single clock cycle when a system error occurs. System errors are described in the PCI Express Base Specification 2.1 or 3.0 in the Root Control register.