DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents

4.3. DisplayPort Intel® FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices

The DisplayPort Intel® FPGA IP hardware design helps you evaluate the functionality of the DisplayPort Intel® FPGA IP and provides a starting point for you to create your own design.
Note: These design examples are available only in the Intel® Quartus® Prime Standard Edition software.
The design example uses a fully functional OpenCore Plus evaluation version, giving you the freedom to explore the core and understand its performance in hardware.

This design performs a loop-through for a standard DisplayPort video stream. You connect a DisplayPort-enabled device—such as a graphics card with DisplayPort interface—to the Transceiver Native PHY RX, and the DisplayPort sink input. The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core. The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data. You require the clock recovery feature to produce video without using a frame buffer. The clock recovery core then sends the video data to the DisplayPort source, and the Transceiver Native PHY TX. The DisplayPort source port of the daughter card transmits the image to a monitor.

The design uses the development board from the following kits:
  • Arria V GX FPGA Starter Kit
  • Cyclone V GT FPGA Development Kit
  • Stratix V GX FPGA Development Kit
Note: If you use another Intel FPGA development board, you must change the device assignments and the pin assignments. You make these changes in the assignments.tcl file. If you use another DisplayPort daughter card, you must change the pin assignments, Platform Designer system, and software.
Figure 5. Hardware Design Overview

The DisplayPort sink uses its internal state machine to negotiate link training upon power up. A Nios II embedded processor performs the source link management; software performs the link training management.

Figure 6. Hardware Design Block Diagram
Table 10.  Clock Source for the Hardware Design
Clock Frequency Description
AUX Clock 16 MHz Used as primary clock source for Auxiliary encoder and decoder. Refer to Source AUX Interface and Sink AUX Interface for more information.
Control Clock 60 MHz Used for Pixel Clock Recovery (PCR) module loop controller and fPLL reconfiguration blocks.
Native PHY Reference Clock 135 MHz Used as Native PHY reference clock for Transceiver CMU PLL.
Video Clock 160 MHz or 300 MHz Video Clock has two functions in this demonstration.
  • rxN_vid_clock for transferring video data from the sink decoder.
  • Input to PCR module as vid_data clock source.
When rxN_vid_clock is used for transferring the sink device's video data and control, the clock frequency must be equal or faster than the upstream device Stream Clock (Strm_Clk) / PIXELS_PER_CLOCK. For example:
  • If the upstream device transmits video data at 1080@60 (Strm_Clk = 148.5 MHz) and the sink device is configured at PIXELS_PER_CLOCK = 1, the device must drive rxN_vid_clk at a minimal frequency of 148.5 MHz.
  • If the sink device is configured at PIXELS_PER_CLOCK = 4, the device must drive rxN_vid_clk at a minimal frequency of 37.125 MHz (148.5 MHz/4).
The DisplayPort hardware demonstration uses the IOPLL to drive rxN_vid_clock with a fixed clock frequency.
  • For designs with HBR2 at PIXELS_PER_CLOCK = 4, the recommended rxN_vid_clock frequency is 160 MHz to support 4K@60 resolution
  • For designs with HBR2 at PIXELS_PER_CLOCK = 2, the recommended rxN_vid_clock frequency is 300 MHz to support 4K@60 resolution
Table 11.  LED FunctionThe development board user LEDs illuminate to indicate the functions described in the table below.
Supported Intel FPGAs Function

This LED indicates that source is successfully lane-trained and is sending video. rxN_vid_locked drives this LED.

This LED turns off if the source is not driving good video.


This LED illuminates for 1-lane designs.


This LED illuminates for 2-lane designs.


This LED illuminates for 4-lane designs.


These LEDs indicate the RX link rate.

  • 00 = RBR
  • 01 = HBR
  • 10 = HBR2
Tip: When creating your own design, note the following design tips:
  • The Bitec HSMC daughter card has inverted transceiver polarity. When creating your own sink (RX) design, use the Invert transceiver polarity option to enable or disable inverted polarity.
  • The DisplayPort standard reverses the RX and TX transceiver channels to minimize noise for one- or two-lane applications. If you create your own design targeting the Bitec daughter card, ensure that the following signals share the same transceiver channel:
    • TX0 and RX3
    • TX1 and RX2
    • TX2 and RX1
    • TX3 and RX0

During operation, you can adjust the DisplayPort source resolution (graphics card) from the PC and observe the effect on the IP core. The Nios II software prints the source and sink AUX channel activity. Press a push-button to print the current TX and RX MSAs.

Refer to the assignments.tcl file for an example of how the channels are assigned in the hardware demonstration.