DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/16/2023
Document Table of Contents EDID Interface

You can use the Avalon® memory-mapped interface EDID interface to access an on-chip memory region containing the sink’s EDID data. The AUX sink controller reads and writes to this memory region according to traffic on the AUX channel.

The Avalon® memory-mapped interface uses an 8-bit address with an 8-bit data bus. The interface assumes a read latency of 1.

Note: The IP core does not instantiate this interface if your design uses a controller to control the sink; for instance, when you turn on the Enable GPU control parameter. Refer to the VESA Enhanced Extended Display Identification Data Implementation Guide for more information.